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authorAnson Huang <b20788@freescale.com>2012-12-05 13:58:34 -0500
committerJason Liu <r64343@freescale.com>2012-12-13 15:11:43 +0800
commit98a5299c945cb7e440e3c3d9c572f017e5a02ede (patch)
treeb13d402770a2e07e41185ad24870260a39942f9c
parent956ae96db2cdcc6e17f0b28aa97484717957b4c8 (diff)
ENGR00235821 mx6: correct work flow of PFDs2009.08-imx6-ts3
PFDs need to be gate/ungate after PLL lock to reset PFDs to right state. Otherwise PFDs may lose correct state in state-machine, then no output clock. For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the bus clock needs it. Signed-off-by: Anson Huang <b20788@freescale.com>
-rw-r--r--cpu/arm_cortexa8/mx6/generic.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c
index 2ee8e1b928d..12cfc511490 100644
--- a/cpu/arm_cortexa8/mx6/generic.c
+++ b/cpu/arm_cortexa8/mx6/generic.c
@@ -1015,6 +1015,37 @@ int arch_cpu_init(void)
{
int val;
+ /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
+ * to make sure PFD is working right, otherwise, PFDs may
+ * not output clock after reset, MX6DL and MX6SL have added 396M pfd
+ * workaround in ROM code, as bus clock need it
+ */
+ writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
+ BM_ANADIG_PFD_480_PFD2_CLKGATE |
+ BM_ANADIG_PFD_480_PFD1_CLKGATE |
+ BM_ANADIG_PFD_480_PFD0_CLKGATE,
+ ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
+ writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
+#ifdef CONFIG_MX6Q
+ BM_ANADIG_PFD_528_PFD2_CLKGATE |
+#endif
+ BM_ANADIG_PFD_528_PFD1_CLKGATE |
+ BM_ANADIG_PFD_528_PFD0_CLKGATE,
+ ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
+
+ writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
+ BM_ANADIG_PFD_480_PFD2_CLKGATE |
+ BM_ANADIG_PFD_480_PFD1_CLKGATE |
+ BM_ANADIG_PFD_480_PFD0_CLKGATE,
+ ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
+ writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
+#ifdef CONFIG_MX6Q
+ BM_ANADIG_PFD_528_PFD2_CLKGATE |
+#endif
+ BM_ANADIG_PFD_528_PFD1_CLKGATE |
+ BM_ANADIG_PFD_528_PFD0_CLKGATE,
+ ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
+
icache_enable();
dcache_enable();