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| author | Igor Opaniuk <igor.opaniuk@toradex.com> | 2019-11-28 15:56:20 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-12-23 10:29:45 +0100 |
| commit | bc138ed0a86f0ca8f870c419955f07f3f21b7dfa (patch) | |
| tree | 1fee96f445772546d1ae25b5a1b90d0b13e81ad1 | |
| parent | 7cdc27b4bb538861185af88dce786221e2789119 (diff) | |
mach-imx: bootaux: add dcache flushing before enabling M4
This patch fixes the issue with broken bootaux command,
when M4 binary is loaded and data cache isn't flushed
before M4 core is enabled.
Reproducing:
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
(submitted upstream https://patchwork.ozlabs.org/patch/1202073/)
| -rw-r--r-- | arch/arm/mach-imx/imx_bootaux.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 97c49536c8..425b12a421 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -27,6 +27,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4); + flush_dcache_all(); + /* Enable M4 */ #ifdef CONFIG_IMX8M call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); |