diff options
| author | Francesco Dolcini <francesco.dolcini@toradex.com> | 2022-06-23 13:53:40 +0200 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2022-06-24 11:53:44 +0200 |
| commit | 01e7ca721a4d0402169518d04532fd9ee29feb25 (patch) | |
| tree | 0995d44c3316a574888b59e636d002c611901a46 | |
| parent | a9545589c0921a8b49316b7e2a21abe66d8dc4c8 (diff) | |
toradex: apalis/colibri_imx6: Fix CLKO1/CLKO2 output
Set CLK01 and CLK02 to 24MHz and enable it in CCM_CCOSR register.
This clock is used by both the audio codec (CLKO1) and by the CSI camera
(CLKO2) and is expected to be 24MHz.
Despite the wrong 16.5MHz there was no real issue because of the wrong
frequency since Linux reconfigures the clocks afterward, however this
was triggering an issue with noise coming from the SGTL5000 audio codec.
The problem is that the SGTL5000 does not have a reset pin and after it
is configured if the input MCLK clock is disabled it produces a constant
noise on its output, this was happening on software reboot.
Forcing the clock to be enabled in U-Boot prevent the problem by making
sure that the clock is always available, without this change as soon as
Linux was changing the clock tree (setting clk_out_sel=1 without setting
clko2_en=1) the noise would start till the actual clock was enabled
(clko2_en=1) during the SGTL5000 driver probe.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
| -rw-r--r-- | board/toradex/apalis_imx6/apalis_imx6.c | 14 | ||||
| -rw-r--r-- | board/toradex/colibri_imx6/colibri_imx6.c | 14 |
2 files changed, 18 insertions, 10 deletions
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 7927caa4c0..fbfb2fb885 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -1056,13 +1056,17 @@ static void ccgr_init(void) /* * Setup CCM_CCOSR register as follows: * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root + * clko2_en = 1 --> CKO2 enabled + * clko2_div = 000 --> divide by 1 + * clko2_sel = 01110 --> osc_clk (24MHz) * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + * clk_out_sel = 1 --> Output CKO2 to CKO1 + * + * This sets both CLKO2/CLKO1 output to 24MHz, + * CLKO1 configuration not relevant because of clk_out_sel + * (CLKO1 set to default) */ - writel(0x000000FB, &ccm->ccosr); + writel(0x010E0101, &ccm->ccosr); } static void ddr_init(int *table, int size) diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index cfb61fa848..b1cb9d023f 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -980,13 +980,17 @@ static void ccgr_init(void) /* * Setup CCM_CCOSR register as follows: * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root + * clko2_en = 1 --> CKO2 enabled + * clko2_div = 000 --> divide by 1 + * clko2_sel = 01110 --> osc_clk (24MHz) * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + * clk_out_sel = 1 --> Output CKO2 to CKO1 + * + * This sets both CLKO2/CLKO1 output to 24MHz, + * CLKO1 configuration not relevant because of clk_out_sel + * (CLKO1 set to default) */ - writel(0x000000FB, &ccm->ccosr); + writel(0x010E0101, &ccm->ccosr); } static void ddr_init(int *table, int size) |