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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2019-05-23 11:52:44 +0800
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-06-20 10:44:09 +0530
commit2b12f6cfe6239d8b6b8c5e7b0c5b5851f7bc489a (patch)
tree6d0ebb01974bb833c5a5be3f379919e7256259f1
parentc16dfd016afb92771d425ae84a2949da1d7e112b (diff)
powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig
Use the Kconfig option to select the PCIe reset errata. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig21
-rw-r--r--include/configs/BSC9132QDS.h1
-rw-r--r--include/configs/C29XPCIE.h1
-rw-r--r--include/configs/MPC8536DS.h1
-rw-r--r--include/configs/MPC8544DS.h1
-rw-r--r--include/configs/MPC8548CDS.h1
-rw-r--r--include/configs/MPC8568MDS.h1
-rw-r--r--include/configs/MPC8569MDS.h1
-rw-r--r--include/configs/MPC8572DS.h1
-rw-r--r--include/configs/P1010RDB.h1
-rw-r--r--include/configs/P1022DS.h1
-rw-r--r--include/configs/P1023RDB.h1
-rw-r--r--include/configs/T208xQDS.h1
-rw-r--r--include/configs/T208xRDB.h1
-rw-r--r--include/configs/UCP1020.h1
-rw-r--r--include/configs/controlcenterd.h1
-rw-r--r--include/configs/p1_p2_rdb_pc.h1
-rw-r--r--include/configs/p1_twr.h1
-rw-r--r--include/configs/sbc8548.h1
-rw-r--r--include/configs/xpedite537x.h1
-rw-r--r--include/configs/xpedite550x.h1
21 files changed, 21 insertions, 20 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 6c3c164883..7572404625 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -533,6 +533,7 @@ config ARCH_BSC9132
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_I2C_A004447
select SYS_FSL_ERRATUM_IFC_A002769
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -551,6 +552,7 @@ config ARCH_C29X
select SYS_FSL_DDR_VER_46
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -566,6 +568,7 @@ config ARCH_MPC8536
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -594,6 +597,7 @@ config ARCH_MPC8544
bool
select FSL_LAW
select SYS_FSL_ERRATUM_A005125
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -609,6 +613,7 @@ config ARCH_MPC8548
select SYS_FSL_ERRATUM_NMG_LBC103
select SYS_FSL_ERRATUM_NMG_ETSEC129
select SYS_FSL_ERRATUM_I2C_A004447
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_SEC
@@ -633,6 +638,7 @@ config ARCH_MPC8560
config ARCH_MPC8568
bool
select FSL_LAW
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -643,6 +649,7 @@ config ARCH_MPC8569
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -657,6 +664,7 @@ config ARCH_MPC8572
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_DDR_115
select SYS_FSL_ERRATUM_DDR111_DDR134
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -681,6 +689,7 @@ config ARCH_P1010
select SYS_FSL_ERRATUM_P1010_A003549
select SYS_FSL_ERRATUM_SEC_A003571
select SYS_FSL_ERRATUM_IFC_A003399
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -718,6 +727,7 @@ config ARCH_P1020
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -738,6 +748,7 @@ config ARCH_P1021
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -759,6 +770,7 @@ config ARCH_P1022
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_SATA_A001
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -772,6 +784,7 @@ config ARCH_P1023
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_I2C_A004447
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -786,6 +799,7 @@ config ARCH_P1024
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -807,6 +821,7 @@ config ARCH_P1025
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -824,6 +839,7 @@ config ARCH_P2020
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_ESDHC_A001
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -1079,6 +1095,7 @@ config ARCH_T2080
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
@@ -1101,6 +1118,7 @@ config ARCH_T2081
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
+ select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
@@ -1437,6 +1455,9 @@ config SYS_P4080_ERRATUM_SERDES_A005
config FSL_PCIE_DISABLE_ASPM
bool
+config FSL_PCIE_RESET
+ bool
+
config SYS_FSL_QORIQ_CHASSIS1
bool
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 1537b45cc1..1c615acb3b 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -57,7 +57,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index e9371a025b..5a1a29bd9e 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -66,7 +66,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 819129033f..7697e8d3e0 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -36,7 +36,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 280b873aee..2cbe855235 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -16,7 +16,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index be600becfe..b37601c794 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -20,7 +20,6 @@
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 5515b9232c..01ee69c013 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -16,7 +16,6 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 3c6661fc83..de187bf9a4 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -15,7 +15,6 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 13fbbb3044..e3952f423b 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -27,7 +27,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 025aa33083..1152bca03b 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -115,7 +115,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 62943a3b0c..4b2eb6525b 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -81,7 +81,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENABLE_36BIT_PHYS
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 7fe34c332e..9535a7bbb2 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -24,7 +24,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#ifndef __ASSEMBLY__
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 98bb3342b9..f09a9ddf3b 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -491,7 +491,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 4b53e19fd4..ab92ca3b68 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -476,7 +476,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index b518c222d4..b8040bb4d9 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -17,7 +17,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_TARTGET_UCP1020T1)
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index f1c3522c68..19223e2947 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -204,7 +204,6 @@
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index d9312bd149..e07d2a178f 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -209,7 +209,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index e42b9b0cb9..1e0708a71b 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -34,7 +34,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 9df8604af7..ba613672eb 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -49,7 +49,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
#ifdef CONFIG_PCIE1
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#endif
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 22dd3c036e..0a87f226f8 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -22,7 +22,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
/*
* Multicore config
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index a7c8dc4e33..0389874609 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -22,7 +22,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
/*
* Multicore config
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-21 01:36:53 +0000