diff options
| author | Vignesh R <vigneshr@ti.com> | 2018-01-24 10:44:06 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2018-01-24 12:11:36 +0530 |
| commit | a743e2ba3837db5e8499b03f0f57c3610d03a570 (patch) | |
| tree | 997cfe2c86fac6eef10c3af4a3d735ddfb354c33 | |
| parent | 948ad4f07598a729a0de523ed3d779115b2fa2f2 (diff) | |
Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"
This reverts commit 57897c13de03ac0136d64641a3eab526c6810387.
Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 26 | ||||
| -rw-r--r-- | include/configs/k2g_evm.h | 1 | ||||
| -rw-r--r-- | include/configs/socfpga_common.h | 1 | ||||
| -rw-r--r-- | include/configs/stv0991.h | 1 |
4 files changed, 6 insertions, 23 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 128c41d715..70d0f431ad 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -30,7 +30,6 @@ #include <linux/errno.h> #include <wait_bit.h> #include <spi.h> -#include <bouncebuf.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US 1 /* 1us */ @@ -722,17 +721,6 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int remaining = n_tx; unsigned int write_bytes; int ret; - struct bounce_buffer bb; - u8 *bb_txbuf; - - /* - * Handle non-4-byte aligned accesses via bounce buffer to - * avoid data abort. - */ - ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ); - if (ret) - return ret; - bb_txbuf = bb.bounce_buffer; /* Configure the indirect read transfer bytes */ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); @@ -743,11 +731,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; - writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); - if (write_bytes % 4) - writesb(plat->ahbbase, - bb_txbuf + rounddown(write_bytes, 4), - write_bytes % 4); + /* Handle non-4-byte aligned access to avoid data abort. */ + if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) + writesb(plat->ahbbase, txbuf, write_bytes); + else + writesl(plat->ahbbase, txbuf, write_bytes >> 2); ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK << @@ -757,7 +745,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, goto failwr; } - bb_txbuf += write_bytes; + txbuf += write_bytes; remaining -= write_bytes; } @@ -768,7 +756,6 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, printf("Indirect write completion error (%i)\n", ret); goto failwr; } - bounce_buffer_stop(&bb); /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE, @@ -779,7 +766,6 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL, plat->regbase + CQSPI_REG_INDIRECTWR); - bounce_buffer_stop(&bb); return ret; } diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 535e7124fc..0a38922a51 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -93,7 +93,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 -#define CONFIG_BOUNCE_BUFFER #endif #define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index ec8bb50050..f6607b101e 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -184,7 +184,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif -#define CONFIG_BOUNCE_BUFFER /* * Designware SPI support diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index fd96979bf8..beb8f1ae9a 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -64,7 +64,6 @@ + */ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 -#define CONFIG_BOUNCE_BUFFER #endif |