arm64: zynqmp: Add board_boot_order for MMC boot extension

In past SPL_ZYNQMP_TWO_SDHCI symbol was introduced to handle boards with
two sdhci controllers. The problem was that U-Boot is registering
controllers based on aliases in DT but bootmode targets specific controller
ID. That's why on boards with one "second" sdhci controller bootmode was
pointing to second controller(MMC2) but alias was setup to mmc0 (the first
controller). And SPL requires to point to mmc0 in this case.

Long time ago commit f101e4bd3703
("spl: add support for alternative boot device") added support for handling
multiple bootmodes in SPL. Use this functionality and setup second sdhci
controller as backup boot device.

Below is table with behavior:
HW/bootmode  bootorder
sd0/sd0      mmc0/mmc1 (mmc1 never called)
sd1/sd1      mmc1/mmc0 (mmc0 fails and mmc1 is called)
sd0+sd1/sd0  mmc0/mmc1 (mmc1 never called)
sd0+sd1/sd1  mmc1/mmc0 (mmc0 never called)

All other bootmodes are not affected but order can be extended to cover
advance boot flows.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

5 files changed, 10 insertions, 18 deletions

diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 6cf17eb94e..d82a737a69 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -117,17 +117,6 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
 config ZYNQ_SDHCI_MAX_FREQ
 	default 200000000
 
-config SPL_ZYNQMP_TWO_SDHCI
-	bool "Enable booting from both SDHCIs"
-	depends on SPL
-	help
-	  This option reflects that board has two SDHCI controllers which
-	  platform can use as boot device. This option ensures that SPL will
-	  setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for
-	  SDHCI0 controller. Platforms which have only one SDHCI controller
-	  shouldn't enable this option because it for software SDHCI0 or SDHCI1
-	  are both covered by BOOT_DEVICE_MMC1.
-
 config SPL_ZYNQMP_ALT_BOOTMODE
 	hex
 	default 0x0 if JTAG_MODE
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index 527646875a..c0398b9116 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -58,6 +58,16 @@ void spl_board_init(void)
 }
 #endif
 
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
+		spl_boot_list[1] = BOOT_DEVICE_MMC2;
+	if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
+
 u32 spl_boot_device(void)
 {
 	u32 reg = 0;
@@ -81,11 +91,7 @@ u32 spl_boot_device(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	case SD_MODE1:
 	case SD1_LSHFT_MODE: /* not working on silicon v1 */
-/* if both controllers enabled, then these two are the second controller */
-#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
 		return BOOT_DEVICE_MMC2;
-/* else, fall through, the one SDHCI controller that is enabled is number 1 */
-#endif
 	case SD_MODE:
 	case EMMC_MODE:
 		return BOOT_DEVICE_MMC1;
diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
index 177558db41..280983d187 100644
--- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
+++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
@@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
diff --git a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
index ba2cbaba58..f206be8a31 100644
--- a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
+++ b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
@@ -9,7 +9,6 @@ CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ZYNQMP_USB=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 7731407118..62c3730515 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_ZYNQMP_USB=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y