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| author | Andrejs Cainikovs <andrejs.cainikovs@toradex.com> | 2022-08-26 13:27:00 +0200 |
|---|---|---|
| committer | Andrejs Cainikovs <andrejs.cainikovs@toradex.com> | 2022-09-23 14:10:40 +0200 |
| commit | 16de213af305ce987d5688429c4b63cc57c48841 (patch) | |
| tree | a64bbe7bff912b17544002797c8fc35f7e4dc590 | |
| parent | e2961d13608ff074033232227a1484f870ad37cc (diff) | |
arm64: dts: imx8mp: add rdc config
Suppress warning by adding default RDC configuration.
Upstream-Status: Inappropriate [other]
- NXP downstream specific
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
| -rw-r--r-- | arch/arm/dts/imx8mp-verdin-u-boot.dtsi | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi index a57ad45ed6..b56deded32 100644 --- a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright 2022 Toradex */ +#include "imx8mp-sec-def.h" #include "imx8mp-u-boot.dtsi" / { @@ -18,6 +19,50 @@ u-boot,dm-spl; wdt = <&wdog1>; }; + + mcu_rdc { + compatible = "imx8m,mcu_rdc"; + /* rdc config when MCU starts + * master + * SDMA3p --> domain 1 + * SDMA3b --> domain 1 + * SDMA3_SPBA2 --> domain 1 + * peripheral: + * SAI3 --> Only domain 1 can access + * UART4 --> Only domain 1 can access + * GPT1 --> Only domain 1 can access + * SDMA3 --> Only domain 1 can access + * I2C3 --> Only domain 1 can access + * memory: + * TCM --> Only domain 1 can access (0x7E0000~0x81FFFF) + * DDR --> Only domain 1 can access (0x80000000~0x81000000) + * end. + */ + start-config = < + RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0 + RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0 + RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0 + RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_I2C3 PDAP_D1_ACCESS 0x0 0x0 + RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS + RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS + 0x0 0x0 0x0 0x0 0x0 + >; + /* rdc config when MCU stops + * memory: + * TCM --> domain 0/1 can access (0x7E0000~0x81FFFF) + * DDR --> domain 0/1 can access (0x80000000~0x81000000) + * end. + */ + stop-config = < + RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS + RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS + 0x0 0x0 0x0 0x0 0x0 + >; + }; }; &clk { |