diff options
| author | Rafael Beims <rafael.beims@toradex.com> | 2025-01-22 14:01:00 -0300 |
|---|---|---|
| committer | Rafael Beims <rafael.beims@toradex.com> | 2025-01-23 06:46:45 -0300 |
| commit | 5d82a9629f6bcd6a197845322e32eb154ccf2b07 (patch) | |
| tree | 2510cd31763dbc2c8acbc1445194ce2f9a373546 | |
| parent | a31fdd543beea5b51af548f7483e34c3d1c3bc73 (diff) | |
verdin-imx8mp: Remove unnecessary pin configuration
The pin MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B is not used on the
Verdin SoM, and having it configured in u-boot breaks Cortex-M use
cases for that pin.
There's no need to send this patch upstream because this pin is already
not configured there.
Upstream-Status: Inappropriate [Other]
Related-to: ELB-6203
Signed-off-by: Rafael Beims <rafael.beims@toradex.com>
| -rw-r--r-- | arch/arm/dts/imx8mp-verdin.dts | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/dts/imx8mp-verdin.dts b/arch/arm/dts/imx8mp-verdin.dts index 4e04d569253..c83e1348e09 100644 --- a/arch/arm/dts/imx8mp-verdin.dts +++ b/arch/arm/dts/imx8mp-verdin.dts @@ -593,7 +593,6 @@ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 @@ -610,7 +609,6 @@ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 @@ -627,7 +625,6 @@ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 |