diff options
| author | Tom Rini <trini@ti.com> | 2013-10-02 11:45:22 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-10-02 11:45:22 -0400 |
| commit | 6297872cd5de4705b6318778261b1f3f64a34c11 (patch) | |
| tree | 7159ac1b03daa6906c8609b2515e42214f3bc422 | |
| parent | 0ae39166b1babbc86da4269458da9bce198bce55 (diff) | |
| parent | f04c53762962280365005c9db12ab561a18f2692 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
112 files changed, 3918 insertions, 1569 deletions
@@ -144,7 +144,6 @@ Directory Hierarchy: /arm1136 Files specific to ARM 1136 CPUs /ixp Files specific to Intel XScale IXP CPUs /pxa Files specific to Intel XScale PXA CPUs - /s3c44b0 Files specific to Samsung S3C44B0 CPUs /sa1100 Files specific to Intel StrongARM SA1100 CPUs /lib Architecture specific library files /avr32 Files generic to AVR32 architecture @@ -5598,15 +5597,17 @@ On ARM, the following registers are used: R0: function argument word/integer result R1-R3: function argument word - R9: GOT pointer - R10: stack limit (used only if stack checking if enabled) + R9: platform specific + R10: stack limit (used only if stack checking is enabled) R11: argument (frame) pointer R12: temporary workspace R13: stack pointer R14: link register R15: program counter - ==> U-Boot will use R8 to hold a pointer to the global data + ==> U-Boot will use R9 to hold a pointer to the global data + + Note: on ARM, only R_ARM_RELATIVE relocations are supported. On Nios II, the ABI is documented here: http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf diff --git a/arch/arm/config.mk b/arch/arm/config.mk index ce3903ba9f..d0cf43ff41 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -16,7 +16,8 @@ endif endif LDFLAGS_FINAL += --gc-sections -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \ + -fno-common -ffixed-r9 -msoft-float # Support generic board on ARM __HAVE_ARCH_GENERIC_BOARD := y @@ -94,7 +95,11 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls endif endif -# check that only R_ARM_RELATIVE relocations are generated ifneq ($(CONFIG_SPL_BUILD),y) -ALL-y += checkarmreloc +# Check that only R_ARM_RELATIVE relocations are generated. +ALL-y += checkarmreloc +# The movt / movw can hardcode 16 bit parts of the addresses in the +# instruction. Relocation is not supported for that case, so disable +# such usage by requiring word relocations. +PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) endif diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index 1ef6061365..b4d396de84 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -4,7 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk index 917da030d6..f4631cb777 100644 --- a/arch/arm/cpu/arm1176/config.mk +++ b/arch/arm/cpu/arm1176/config.mk @@ -4,7 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v6. PLATFORM_CPPFLAGS += -march=armv5t diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk index 56b6280d5a..2581f0ae67 100644 --- a/arch/arm/cpu/arm720t/config.mk +++ b/arch/arm/cpu/arm720t/config.mk @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi # ========================================================================= # diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk index 58fd756586..67537dcedc 100644 --- a/arch/arm/cpu/arm920t/config.mk +++ b/arch/arm/cpu/arm920t/config.mk @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= # diff --git a/arch/arm/cpu/arm925t/config.mk b/arch/arm/cpu/arm925t/config.mk index 58fd756586..67537dcedc 100644 --- a/arch/arm/cpu/arm925t/config.mk +++ b/arch/arm/cpu/arm925t/config.mk @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= # diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 917ff7edec..12b0d09d37 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= # diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c index 8db2a67f37..629b727745 100644 --- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c +++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c @@ -38,5 +38,10 @@ int main(void) DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); + DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, gpcr)); + DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, fmcr)); + return 0; } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 0392afd9be..68c30afc48 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -102,8 +102,9 @@ static uint8_t mxs_get_bootmode_index(void) return i; } -void mxs_common_spl_init(const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size) +void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, + const iomux_cfg_t *iomux_setup, + const unsigned int iomux_size) { struct mxs_spl_data *data = (struct mxs_spl_data *) ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index f357959059..4275c5d0a6 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -14,6 +14,13 @@ #include "mxs_init.h" +/** + * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL + * + * This function switches the CPU core clock from PLL to 24MHz XTAL + * oscilator. This is necessary if the PLL is being reconfigured to + * prevent crash of the CPU core. + */ static void mxs_power_clock2xtal(void) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -24,6 +31,13 @@ static void mxs_power_clock2xtal(void) &clkctrl_regs->hw_clkctrl_clkseq_set); } +/** + * mxs_power_clock2pll() - Switch CPU core clock source to PLL + * + * This function switches the CPU core clock from 24MHz XTAL oscilator + * to PLL. This can only be called once the PLL has re-locked and once + * the PLL is stable after reconfiguration. + */ static void mxs_power_clock2pll(void) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -36,6 +50,13 @@ static void mxs_power_clock2pll(void) CLKCTRL_CLKSEQ_BYPASS_CPU); } +/** + * mxs_power_set_auto_restart() - Set the auto-restart bit + * + * This function ungates the RTC block and sets the AUTO_RESTART + * bit to work around a design bug on MX28EVK Rev. A . + */ + static void mxs_power_set_auto_restart(void) { struct mxs_rtc_regs *rtc_regs = @@ -66,6 +87,14 @@ static void mxs_power_set_auto_restart(void) ; } +/** + * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter + * + * This function configures the VDDIO, VDDA and VDDD linear regulators output + * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching + * converter. This is the recommended setting for the case where we use both + * linear regulators and DC-DC converter to power the VDDIO rail. + */ static void mxs_power_set_linreg(void) { struct mxs_power_regs *power_regs = @@ -85,6 +114,11 @@ static void mxs_power_set_linreg(void) POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); } +/** + * mxs_get_batt_volt() - Measure battery input voltage + * + * This function retrieves the battery input voltage and returns it. + */ static int mxs_get_batt_volt(void) { struct mxs_power_regs *power_regs = @@ -96,11 +130,24 @@ static int mxs_get_batt_volt(void) return volt; } +/** + * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot + * + * This function checks if the battery input voltage is higher than 3.6V and + * therefore allows the system to successfully boot using this power source. + */ static int mxs_is_batt_ready(void) { return (mxs_get_batt_volt() >= 3600); } +/** + * mxs_is_batt_good() - Test if battery is operational at all + * + * This function starts recharging the battery and tests if the input current + * provided by the 5V input recharging the battery is also sufficient to power + * the DC-DC converter. + */ static int mxs_is_batt_good(void) { struct mxs_power_regs *power_regs = @@ -141,6 +188,15 @@ static int mxs_is_batt_good(void) return 0; } +/** + * mxs_power_setup_5v_detect() - Start the 5V input detection comparator + * + * This function enables the 5V detection comparator and sets the 5V valid + * threshold to 4.4V . We use 4.4V threshold here to make sure that even + * under high load, the voltage drop on the 5V input won't be so critical + * to cause undervolt on the 4P2 linear regulator supplying the DC-DC + * converter and thus making the system crash. + */ static void mxs_power_setup_5v_detect(void) { struct mxs_power_regs *power_regs = @@ -153,6 +209,12 @@ static void mxs_power_setup_5v_detect(void) POWER_5VCTRL_PWRUP_VBUS_CMPS); } +/** + * mxs_src_power_init() - Preconfigure the power block + * + * This function configures reasonable values for the DC-DC control loop + * and battery monitor. + */ static void mxs_src_power_init(void) { struct mxs_power_regs *power_regs = @@ -184,6 +246,12 @@ static void mxs_src_power_init(void) clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); } +/** + * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator + * + * This function configures the necessary parameters for the 4P2 linear + * regulator to supply the DC-DC converter from 5V input. + */ static void mxs_power_init_4p2_params(void) { struct mxs_power_regs *power_regs = @@ -208,6 +276,12 @@ static void mxs_power_init_4p2_params(void) 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } +/** + * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2 + * @xfer: Select if the input shall be enabled or disabled + * + * This function enables or disables the 4P2 input into the DC-DC converter. + */ static void mxs_enable_4p2_dcdc_input(int xfer) { struct mxs_power_regs *power_regs = @@ -304,6 +378,12 @@ static void mxs_enable_4p2_dcdc_input(int xfer) POWER_CTRL_ENIRQ_VDD5V_DROOP); } +/** + * mxs_power_init_4p2_regulator() - Start the 4P2 regulator + * + * This function enables the 4P2 regulator and switches the DC-DC converter + * to use the 4P2 input. + */ static void mxs_power_init_4p2_regulator(void) { struct mxs_power_regs *power_regs = @@ -388,6 +468,12 @@ static void mxs_power_init_4p2_regulator(void) writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); } +/** + * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source + * + * This function configures the DC-DC converter to be supplied from the 4P2 + * linear regulator. + */ static void mxs_power_init_dcdc_4p2_source(void) { struct mxs_power_regs *power_regs = @@ -410,6 +496,12 @@ static void mxs_power_init_dcdc_4p2_source(void) } } +/** + * mxs_power_enable_4p2() - Power up the 4P2 regulator + * + * This function drives the process of powering up the 4P2 linear regulator + * and switching the DC-DC converter input over to the 4P2 linear regulator. + */ static void mxs_power_enable_4p2(void) { struct mxs_power_regs *power_regs = @@ -469,6 +561,14 @@ static void mxs_power_enable_4p2(void) &power_regs->hw_power_charge_clr); } +/** + * mxs_boot_valid_5v() - Boot from 5V supply + * + * This function configures the power block to boot from valid 5V input. + * This is called only if the 5V is reliable and can properly supply the + * CPU. This function proceeds to configure the 4P2 converter to be supplied + * from the 5V input. + */ static void mxs_boot_valid_5v(void) { struct mxs_power_regs *power_regs = @@ -492,6 +592,11 @@ static void mxs_boot_valid_5v(void) mxs_power_enable_4p2(); } +/** + * mxs_powerdown() - Shut down the system + * + * This function powers down the CPU completely. + */ static void mxs_powerdown(void) { struct mxs_power_regs *power_regs = @@ -501,6 +606,12 @@ static void mxs_powerdown(void) &power_regs->hw_power_reset); } +/** + * mxs_batt_boot() - Configure the power block to boot from battery input + * + * This function configures the power block to boot from the battery voltage + * supply. + */ static void mxs_batt_boot(void) { struct mxs_power_regs *power_regs = @@ -545,6 +656,14 @@ static void mxs_batt_boot(void) 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } +/** + * mxs_handle_5v_conflict() - Test if the 5V input is reliable + * + * This function tests if the 5V input can reliably supply the system. If it + * can, then proceed to configuring the system to boot from 5V source, otherwise + * try booting from battery supply. If we can not boot from battery supply + * either, shut down the system. + */ static void mxs_handle_5v_conflict(void) { struct mxs_power_regs *power_regs = @@ -581,6 +700,12 @@ static void mxs_handle_5v_conflict(void) } } +/** + * mxs_5v_boot() - Configure the power block to boot from 5V input + * + * This function handles configuration of the power block when supplied by + * a 5V input. + */ static void mxs_5v_boot(void) { struct mxs_power_regs *power_regs = @@ -604,6 +729,12 @@ static void mxs_5v_boot(void) mxs_handle_5v_conflict(); } +/** + * mxs_init_batt_bo() - Configure battery brownout threshold + * + * This function configures the battery input brownout threshold. The value + * at which the battery brownout happens is configured to 3.0V in the code. + */ static void mxs_init_batt_bo(void) { struct mxs_power_regs *power_regs = @@ -618,6 +749,12 @@ static void mxs_init_batt_bo(void) writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); } +/** + * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter + * + * This function turns off the VDDD linear regulator and therefore makes + * the VDDD rail be supplied only by the DC-DC converter. + */ static void mxs_switch_vddd_to_dcdc_source(void) { struct mxs_power_regs *power_regs = @@ -632,6 +769,15 @@ static void mxs_switch_vddd_to_dcdc_source(void) POWER_VDDDCTRL_DISABLE_STEPPING); } +/** + * mxs_power_configure_power_source() - Configure power block source + * + * This function is the core of the power configuration logic. The function + * selects the power block input source and configures the whole power block + * accordingly. After the configuration is complete and the system is stable + * again, the function switches the CPU clock source back to PLL. Finally, + * the function switches the voltage rails to DC-DC converter. + */ static void mxs_power_configure_power_source(void) { int batt_ready, batt_good; @@ -676,6 +822,15 @@ static void mxs_power_configure_power_source(void) #endif } +/** + * mxs_enable_output_rail_protection() - Enable power rail protection + * + * This function enables overload protection on the power rails. This is + * triggered if the power rails' voltage drops rapidly due to overload and + * in such case, the supply to the powerrail is cut-off, protecting the + * CPU from damage. Note that under such condition, the system will likely + * crash or misbehave. + */ static void mxs_enable_output_rail_protection(void) { struct mxs_power_regs *power_regs = @@ -694,6 +849,13 @@ static void mxs_enable_output_rail_protection(void) POWER_VDDIOCTRL_PWDN_BRNOUT); } +/** + * mxs_get_vddio_power_source_off() - Get VDDIO rail power source + * + * This function tests if the VDDIO rail is supplied by linear regulator + * or by the DC-DC converter. Returns 1 if powered by linear regulator, + * returns 0 if powered by the DC-DC converter. + */ static int mxs_get_vddio_power_source_off(void) { struct mxs_power_regs *power_regs = @@ -722,6 +884,13 @@ static int mxs_get_vddio_power_source_off(void) } +/** + * mxs_get_vddd_power_source_off() - Get VDDD rail power source + * + * This function tests if the VDDD rail is supplied by linear regulator + * or by the DC-DC converter. Returns 1 if powered by linear regulator, + * returns 0 if powered by the DC-DC converter. + */ static int mxs_get_vddd_power_source_off(void) { struct mxs_power_regs *power_regs = @@ -810,6 +979,18 @@ static const struct mxs_vddx_cfg mxs_vddmem_cfg = { }; #endif +/** + * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail + * @cfg: Configuration data of the DC-DC converter rail + * @new_target: New target voltage of the DC-DC converter rail + * @new_brownout: New brownout trigger voltage + * + * This function configures the output voltage on the DC-DC converter rail. + * The rail is selected by the @cfg argument. The new voltage target is + * selected by the @new_target and the voltage is specified in mV. The + * new brownout value is selected by the @new_brownout argument and the + * value is also in mV. + */ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, uint32_t new_target, uint32_t new_brownout) { @@ -883,6 +1064,14 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, } } +/** + * mxs_setup_batt_detect() - Start the battery voltage measurement logic + * + * This function starts and configures the LRADC block. This allows the + * power initialization code to measure battery voltage and based on this + * knowledge, decide whether to boot at all, boot from battery or boot + * from 5V input. + */ static void mxs_setup_batt_detect(void) { mxs_lradc_init(); @@ -890,6 +1079,14 @@ static void mxs_setup_batt_detect(void) early_delay(10); } +/** + * mxs_ungate_power() - Ungate the POWER block + * + * This function ungates clock to the power block. In case the power block + * was still gated at this point, it will not be possible to configure the + * block and therefore the power initialization would fail. This function + * is only needed on i.MX233, on i.MX28 the power block is always ungated. + */ static void mxs_ungate_power(void) { #ifdef CONFIG_MX23 @@ -900,6 +1097,12 @@ static void mxs_ungate_power(void) #endif } +/** + * mxs_power_init() - The power block init main function + * + * This function calls all the power block initialization functions in + * proper sequence to start the power block. + */ void mxs_power_init(void) { struct mxs_power_regs *power_regs = @@ -933,6 +1136,12 @@ void mxs_power_init(void) } #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT +/** + * mxs_power_wait_pswitch() - Wait for power switch to be pressed + * + * This function waits until the power-switch was pressed to start booting + * the board. + */ void mxs_power_wait_pswitch(void) { struct mxs_power_regs *power_regs = diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 94b2b3fd30..3e454ae1bc 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -152,39 +152,49 @@ _reset: /* * Store all registers on old stack pointer, this will allow us later to * return to the BootROM and let the BootROM load U-Boot into RAM. + * + * WARNING: Register r0 and r1 are used by the BootROM to pass data + * to the called code. Register r0 will contain arbitrary + * data that are set in the BootStream. In case this code + * was started with CALL instruction, register r1 will contain + * pointer to the return value this function can then set. + * The code below MUST NOT CHANGE register r0 and r1 ! */ push {r0-r12,r14} - /* save control register c1 */ - mrc p15, 0, r0, c1, c0, 0 - push {r0} + /* Save control register c1 */ + mrc p15, 0, r2, c1, c0, 0 + push {r2} - /* - * set the cpu to SVC32 mode and store old CPSR register content - */ - mrs r0,cpsr - push {r0} - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 + /* Set the cpu to SVC32 mode and store old CPSR register content. */ + mrs r2, cpsr + push {r2} + bic r2, r2, #0x1f + orr r2, r2, #0xd3 + msr cpsr, r2 bl board_init_ll + /* Restore BootROM's CPU mode (especially FIQ). */ + pop {r2} + msr cpsr,r2 + /* - * restore bootrom's cpu mode (especially FIQ) + * Restore c1 register. Especially set exception vector location + * back to BootROM space which is required by bootrom for USB boot. */ - pop {r0} - msr cpsr,r0 + pop {r2} + mcr p15, 0, r2, c1, c0, 0 + + pop {r0-r12,r14} /* - * restore c1 register - * (especially set exception vector location back to - * bootrom space which is required by bootrom for USB boot) + * In case this code was started by the CALL instruction, the register + * r0 is examined by the BootROM after this code returns. The value in + * r0 must be set to 0 to indicate successful return. */ - pop {r0} - mcr p15, 0, r0, c1, c0, 0 + mov r0, #0 - pop {r0-r12,r14} bx lr _hang: diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk index 1e41c11686..eb81a5708d 100644 --- a/arch/arm/cpu/arm946es/config.mk +++ b/arch/arm/cpu/arm946es/config.mk @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= # diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk index 1e41c11686..eb81a5708d 100644 --- a/arch/arm/cpu/arm_intcm/config.mk +++ b/arch/arm/cpu/arm_intcm/config.mk @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 # ========================================================================= # diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 2ea3d698fb..a31bf40e5b 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -27,6 +27,7 @@ #include <miiphy.h> #include <cpsw.h> #include <asm/errno.h> +#include <linux/compiler.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <linux/usb/musb.h> @@ -137,6 +138,16 @@ int arch_misc_init(void) } #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) +/* + * This function is the place to do per-board things such as ramp up the + * MPU clock frequency. + */ +__weak void am33xx_spl_board_init(void) +{ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + static void rtc32k_enable(void) { struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index e5f287b338..fabe2595a3 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = { .cm_div_m2_dpll = CM_WKUP + 0xA0, }; -const struct dpll_params dpll_mpu = { +struct dpll_params dpll_mpu_opp100 = { CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { +const struct dpll_params dpll_core_opp100 = { 1000, OSC-1, -1, -1, 10, 8, 4}; +const struct dpll_params dpll_mpu = { + MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_core = { + 50, OSC-1, -1, -1, 1, 1, 1}; const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1}; diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 63afaaa328..50eb598ff2 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> +#include <power/tps65910.h> struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; @@ -119,3 +120,59 @@ int print_cpuinfo(void) return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_AM33XX +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev) +{ + int sil_rev; + + sil_rev = readl(&cdev->deviceid) >> 28; + + if (sil_rev == 1) + /* PG 2.0, efuse may not be set. */ + return MPUPLL_M_800; + else if (sil_rev >= 2) { + /* Check what the efuse says our max speed is. */ + int efuse_arm_mpu_max_freq; + efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma); + switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) { + case AM335X_ZCZ_1000: + return MPUPLL_M_1000; + case AM335X_ZCZ_800: + return MPUPLL_M_800; + case AM335X_ZCZ_720: + return MPUPLL_M_720; + case AM335X_ZCZ_600: + case AM335X_ZCE_600: + return MPUPLL_M_600; + case AM335X_ZCZ_300: + case AM335X_ZCE_300: + return MPUPLL_M_300; + } + } + + /* PG 1.0 or otherwise unknown, use the PG1.0 max */ + return MPUPLL_M_720; +} + +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) +{ + /* For PG2.1 and later, we have one set of values. */ + if (sil_rev >= 2) { + switch (frequency) { + case MPUPLL_M_1000: + return TPS65910_OP_REG_SEL_1_3_2_5; + case MPUPLL_M_800: + return TPS65910_OP_REG_SEL_1_2_6; + case MPUPLL_M_720: + return TPS65910_OP_REG_SEL_1_2_0; + case MPUPLL_M_600: + case MPUPLL_M_300: + return TPS65910_OP_REG_SEL_1_1_3; + } + } + + /* Default to PG1.0/PG2.0 values. */ + return TPS65910_OP_REG_SEL_1_1_3; +} +#endif diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index ca4a9e72c0..f0d9c04327 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -4,7 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # If armv7-a is not supported by GCC fall-back to armv5, which is # supported by more tool-chains diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 82b2b86520..69e3053a42 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -22,11 +22,11 @@ ENTRY(lowlevel_init) ldr sp, =CONFIG_SYS_INIT_SP_ADDR bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #ifdef CONFIG_SPL_BUILD - ldr r8, =gdata + ldr r9, =gdata #else sub sp, #GD_SIZE bic sp, sp, #7 - mov r8, sp + mov r9, sp #endif /* * Save the old lr(passed in ip) and the current lr to stack diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 7efb0d209a..df11678609 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -228,13 +228,13 @@ static u32 get_axi_clk(void) static u32 get_emi_slow_clk(void) { - u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0; + u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0; cscmr1 = __raw_readl(&imx_ccm->cscmr1); emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; - emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; - emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; + emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; + emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET; switch (emi_clk_sel) { case 0: @@ -251,7 +251,7 @@ static u32 get_emi_slow_clk(void) break; } - return root_freq / (emi_slow_pof + 1); + return root_freq / (emi_slow_podf + 1); } #ifdef CONFIG_MX6SL @@ -282,6 +282,36 @@ static u32 get_mmdc_ch0_clk(void) return freq / (podf + 1); } + +int enable_fec_anatop_clock(void) +{ + u32 reg = 0; + s32 timeout = 100000; + + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + reg = readl(&anatop->pll_enet); + if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || + (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { + reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; + writel(reg, &anatop->pll_enet); + while (timeout--) { + if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) + break; + } + if (timeout < 0) + return -ETIMEDOUT; + } + + /* Enable FEC clock */ + reg |= BM_ANADIG_PLL_ENET_ENABLE; + reg &= ~BM_ANADIG_PLL_ENET_BYPASS; + writel(reg, &anatop->pll_enet); + + return 0; +} + #else static u32 get_mmdc_ch0_clk(void) { @@ -457,7 +487,7 @@ void enable_ipu_clock(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; writel(reg, &mxc_ccm->CCGR3); } /***************************************************/ diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 6b4772b684..0ffa03ac01 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -76,6 +76,9 @@ void spl_board_init(void) #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif +#ifdef CONFIG_AM33XX + am33xx_spl_board_init(); +#endif } int board_mmc_init(bd_t *bis) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 7580594074..ab0c5680f5 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores) val = optimize_vcore_voltage(&vcores->iva); do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); - - if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { - /* Configure LDO SRAM "magic" bits */ - writel(2, (*prcm)->prm_sldo_core_setup); - writel(2, (*prcm)->prm_sldo_mpu_setup); - writel(2, (*prcm)->prm_sldo_mm_setup); - } } static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 579818d559..5a3d52c11a 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = { .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, - .prm_sldo_core_setup = 0x4ae07bc4, - .prm_sldo_core_ctrl = 0x4ae07bc8, - .prm_sldo_mpu_setup = 0x4ae07bcc, - .prm_sldo_mpu_ctrl = 0x4ae07bd0, - .prm_sldo_mm_setup = 0x4ae07bd4, - .prm_sldo_mm_ctrl = 0x4ae07bd8, /* SCRM stuff, used by some boards */ .scrm_auxclk0 = 0x4ae0a310, @@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = { .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, - .prm_sldo_core_setup = 0x4ae07cc4, - .prm_sldo_core_ctrl = 0x4ae07cc8, - .prm_sldo_mpu_setup = 0x4ae07ccc, - .prm_sldo_mpu_ctrl = 0x4ae07cd0, - .prm_sldo_mm_setup = 0x4ae07cd4, - .prm_sldo_mm_ctrl = 0x4ae07cd8, .prm_abbldo_mpu_setup = 0x4ae07cdc, .prm_abbldo_mpu_ctrl = 0x4ae07ce0, diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk index 4f01610868..3a36ab65e1 100644 --- a/arch/arm/cpu/armv7/rmobile/config.mk +++ b/arch/arm/cpu/armv7/rmobile/config.mk @@ -4,7 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v7a. PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c index 0133565299..3b8d9497a0 100644 --- a/arch/arm/cpu/armv7/zynq/timer.c +++ b/arch/arm/cpu/armv7/zynq/timer.c @@ -57,7 +57,7 @@ int timer_init(void) SCUTIMER_CONTROL_ENABLE_MASK; /* Load the timer counter register */ - writel(0xFFFFFFFF, &timer_base->counter); + writel(0xFFFFFFFF, &timer_base->load); /* * Start the A9Timer device diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk index 0f12f8b1c7..fd47c60939 100644 --- a/arch/arm/cpu/ixp/config.mk +++ b/arch/arm/cpu/ixp/config.mk @@ -8,7 +8,7 @@ BIG_ENDIAN = y -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian +PLATFORM_RELFLAGS += -mbig-endian PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index 535bca3e9f..d8d263d404 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -mcpu=xscale # ========================================================================= # diff --git a/arch/arm/cpu/s3c44b0/cache.c b/arch/arm/cpu/s3c44b0/cache.c deleted file mode 100644 index aeee02d85d..0000000000 --- a/arch/arm/cpu/s3c44b0/cache.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/hardware.h> - -static void s3c44b0_flush_cache(void) -{ - volatile int i; - /* flush cycle */ - for(i=0x10002000;i<0x10004800;i+=16) - { - *((int *)i)=0x0; - } -} - -void icache_enable (void) -{ - ulong reg; - - s3c44b0_flush_cache(); - - /* - Init cache - Non-cacheable area (everything outside RAM) - 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; - - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; -} - -void icache_disable (void) -{ - ulong reg; - - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; -} - -int icache_status (void) -{ - return 0; -} - -void dcache_enable (void) -{ - icache_enable(); -} - -void dcache_disable (void) -{ - icache_disable(); -} - -int dcache_status (void) -{ - return dcache_status(); -} diff --git a/arch/arm/cpu/s3c44b0/config.mk b/arch/arm/cpu/s3c44b0/config.mk deleted file mode 100644 index b902ca36a8..0000000000 --- a/arch/arm/cpu/s3c44b0/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/s3c44b0/cpu.c b/arch/arm/cpu/s3c44b0/cpu.c deleted file mode 100644 index fa931503a0..0000000000 --- a/arch/arm/cpu/s3c44b0/cpu.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * S3C44B0 CPU specific code - */ - -#include <common.h> -#include <command.h> -#include <asm/hardware.h> - -int arch_cpu_init (void) -{ - icache_enable(); - - return 0; -} - -int cleanup_before_linux (void) -{ - /* - cache memory should be enabled before calling - Linux to make the kernel uncompression faster - */ - icache_enable(); - - disable_interrupts (); - - return 0; -} - -void reset_cpu (ulong addr) -{ - /* - reset the cpu using watchdog - */ - - /* Disable the watchdog.*/ - WTCON&=~(1<<5); - - /* set the timeout value to a short time... */ - WTCNT = 0x1; - - /* Enable the watchdog. */ - WTCON|=1; - WTCON|=(1<<5); - - while(1) { - /*NOP*/ - } -} diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S deleted file mode 100644 index 6a59592f4c..0000000000 --- a/arch/arm/cpu/s3c44b0/start.S +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Startup Code for S3C44B0 CPU-core - * - * (C) Copyright 2004 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <version.h> - -/* - * Jump vector table - */ - - -.globl _start -_start: b reset - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate u-boot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - bl lowlevel_init -#endif - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - bx lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -#define INTCON (0x01c00000+0x200000) -#define INTMSK (0x01c00000+0x20000c) -#define LOCKTIME (0x01c00000+0x18000c) -#define PLLCON (0x01c00000+0x180000) -#define CLKCON (0x01c00000+0x180004) -#define WTCON (0x01c00000+0x130000) -cpu_init_crit: - /* disable watch dog */ - ldr r0, =WTCON - ldr r1, =0x0 - str r1, [r0] - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - ldr r1,=INTMSK - ldr r0, =0x03fffeff - str r0, [r1] - - ldr r1, =INTCON - ldr r0, =0x05 - str r0, [r1] - - /* Set Clock Control Register */ - ldr r1, =LOCKTIME - ldrb r0, =800 - strb r0, [r1] - - ldr r1, =PLLCON - -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - - str r0, [r1] - - ldr r1,=CLKCON - ldr r0, =0x7ff8 - str r0, [r1] - - mov pc, lr - - -/*************************************************/ -/* interrupt vectors */ -/*************************************************/ -real_vectors: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/*************************************************/ - -undefined_instruction: - mov r6, #3 - b reset - -software_interrupt: - mov r6, #4 - b reset - -prefetch_abort: - mov r6, #5 - b reset - -data_abort: - mov r6, #6 - b reset - -not_used: - /* we *should* never reach this */ - mov r6, #7 - b reset - -irq: - mov r6, #8 - b reset - -fiq: - mov r6, #9 - b reset diff --git a/arch/arm/cpu/s3c44b0/timer.c b/arch/arm/cpu/s3c44b0/timer.c deleted file mode 100644 index f25af7a390..0000000000 --- a/arch/arm/cpu/s3c44b0/timer.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/hardware.h> - -/* we always count down the max. */ -#define TIMER_LOAD_VAL 0xffff - -/* macro to read the 16 bit timer */ -#define READ_TIMER (TCNTO1 & 0xffff) - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ NOT supported -#endif - -static ulong timestamp; -static ulong lastdec; - -int timer_init (void) -{ - TCFG0 = 0x000000E9; - TCFG1 = 0x00000004; - TCON = 0x00000900; - TCNTB1 = TIMER_LOAD_VAL; - TCMPB1 = 0; - TCON = 0x00000B00; - TCON = 0x00000900; - - - lastdec = TCNTB1 = TIMER_LOAD_VAL; - timestamp = 0; - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void __udelay (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 8; - - tmo += get_timer (0); - - while (get_timer_masked () < tmo) - /*NOP*/; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 8; - } else { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*8); - } - - endtime = get_timer(0) + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk index 576f685c58..b3026cc50d 100644 --- a/arch/arm/cpu/sa1100/config.mk +++ b/arch/arm/cpu/sa1100/config.mk @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 # ========================================================================= # diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 140379fb38..02ed5957e9 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -11,9 +11,17 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ +/* MAIN PLL Fdll supported frequencies */ +#define MPUPLL_M_1000 1000 +#define MPUPLL_M_800 800 +#define MPUPLL_M_720 720 +#define MPUPLL_M_600 600 +#define MPUPLL_M_550 550 +#define MPUPLL_M_300 300 + /* MAIN PLL Fdll = 550 MHz, by default */ #ifndef CONFIG_SYS_MPUCLK -#define CONFIG_SYS_MPUCLK 550 +#define CONFIG_SYS_MPUCLK MPUPLL_M_550 #endif #define UART_RESET (0x1 << 1) @@ -21,5 +29,7 @@ #define UART_SMART_IDLE_EN (0x1 << 0x3) extern void enable_dmm_clocks(void); +extern const struct dpll_params dpll_core_opp100; +extern struct dpll_params dpll_mpu_opp100; #endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 73e6db8998..52fa128af9 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -38,6 +38,16 @@ #define AM335X 0xB944 #define TI81XX 0xB81E #define DEVICE_ID (CTRL_BASE + 0x0600) +#define DEVICE_ID_MASK 0x1FFF + +/* MPU max frequencies */ +#define AM335X_ZCZ_300 0x1FEF +#define AM335X_ZCZ_600 0x1FAF +#define AM335X_ZCZ_720 0x1F2F +#define AM335X_ZCZ_800 0x1E2F +#define AM335X_ZCZ_1000 0x1C2F +#define AM335X_ZCE_300 0x1FDF +#define AM335X_ZCE_600 0x1F9F /* This gives the status of the boot mode pins on the evm */ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ @@ -509,6 +519,8 @@ struct ctrl_dev { unsigned int macid1h; /* offset 0x3c */ unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ + unsigned int resv5[106]; + unsigned int efuse_sma; /* offset 0x1FC */ }; /* gmii_sel register defines */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index c6070a3fc9..87b7d367b9 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -10,6 +10,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include <asm/arch/cpu.h> #define BOARD_REV_ID 0x0 @@ -42,4 +43,7 @@ u32 wait_on_value(u32, u32, void *, u32); #ifdef CONFIG_NOR_BOOT void enable_norboot_pin_mux(void); #endif +void am33xx_spl_board_init(void); +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); #endif diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index a27145ba28..92c847e44a 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -169,7 +169,7 @@ struct iim_regs { struct fuse_bank { u32 fuse_regs[0x20]; u32 fuse_rsvd[0xe0]; - } bank[1]; + } bank[2]; }; struct fuse_bank0_regs { @@ -209,9 +209,13 @@ struct fuse_bank0_regs { #define IIM_BASE_ADDR IMX_IIM_BASE #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) +#define IMX_NFC_BASE (0xD8000000) #define IMX_ESD_BASE (0xD8001000) #define IMX_WEIM_BASE (0xD8002000) +#define NFC_BASE_ADDR IMX_NFC_BASE + + /* FMCR System Control bit definition*/ #define UART4_RXD_CTL (1 << 25) #define UART4_RTS_CTL (1 << 24) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index c49368765b..93f29a780f 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -50,4 +50,5 @@ void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); +int enable_fec_anatop_clock(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe60f4..2813593e25 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -892,7 +892,7 @@ struct mxc_ccm_reg { #define PLL2_PFD0_FREQ 352000000 #define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 400000000 +#define PLL2_PFD2_FREQ 396000000 #define PLL2_PFD2_DIV_FREQ 200000000 #define PLL3_PFD0_FREQ 720000000 #define PLL3_PFD1_FREQ 540000000 diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index f4cfd4f921..ff13a1ea9f 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -27,6 +27,11 @@ #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) +#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) +#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) +#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ + | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) + #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index c3d0b70877..b5df68afc6 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -235,7 +235,7 @@ enum { MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), @@ -309,7 +309,7 @@ enum { MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT2__LCDIF_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), @@ -1043,7 +1043,7 @@ enum { MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), - MX6_PAD_GPIO_1__USBOTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), + MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index 94df0075b0..fe9a8c343d 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -984,6 +984,7 @@ enum { MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), + MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index b39a354f39..5f9c90ad87 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -18,5 +18,17 @@ enum { MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), + + MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0), + MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0), + MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0), + MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0), + MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0), + MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0), + MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0), + MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0), + MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), + MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 1038592c92..43c7dd6bf1 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -28,8 +28,9 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); #include <asm/arch/iomux-mx28.h> #endif -void mxs_common_spl_init(const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size); +void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, + const iomux_cfg_t *iomux_setup, + const unsigned int iomux_size); #endif struct mxs_pair { diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h deleted file mode 100644 index 146e265d9a..0000000000 --- a/arch/arm/include/asm/arch-s3c44b0/hardware.h +++ /dev/null @@ -1,281 +0,0 @@ -/********************************************************/ -/* */ -/* Samsung S3C44B0 */ -/* tpu <tapu@371.net> */ -/* */ -/********************************************************/ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#define REGBASE 0x01c00000 -#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) -#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) -#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) - - -/*****************************/ -/* CPU Wrapper Registers */ -/*****************************/ - -#define SYSCFG REGL(0x000000) -#define NCACHBE0 REGL(0x000004) -#define NCACHBE1 REGL(0x000008) -#define SBUSCON REGL(0x040000) - -/************************************/ -/* Memory Controller Registers */ -/************************************/ - -#define BWSCON REGL(0x080000) -#define BANKCON0 REGL(0x080004) -#define BANKCON1 REGL(0x080008) -#define BANKCON2 REGL(0x08000c) -#define BANKCON3 REGL(0x080010) -#define BANKCON4 REGL(0x080014) -#define BANKCON5 REGL(0x080018) -#define BANKCON6 REGL(0x08001c) -#define BANKCON7 REGL(0x080020) -#define REFRESH REGL(0x080024) -#define BANKSIZE REGL(0x080028) -#define MRSRB6 REGL(0x08002c) -#define MRSRB7 REGL(0x080030) - -/*********************/ -/* UART Registers */ -/*********************/ - -#define ULCON0 REGL(0x100000) -#define ULCON1 REGL(0x104000) -#define UCON0 REGL(0x100004) -#define UCON1 REGL(0x104004) -#define UFCON0 REGL(0x100008) -#define UFCON1 REGL(0x104008) -#define UMCON0 REGL(0x10000c) -#define UMCON1 REGL(0x10400c) -#define UTRSTAT0 REGL(0x100010) -#define UTRSTAT1 REGL(0x104010) -#define UERSTAT0 REGL(0x100014) -#define UERSTAT1 REGL(0x104014) -#define UFSTAT0 REGL(0x100018) -#define UFSTAT1 REGL(0x104018) -#define UMSTAT0 REGL(0x10001c) -#define UMSTAT1 REGL(0x10401c) -#define UTXH0 REGB(0x100020) -#define UTXH1 REGB(0x104020) -#define URXH0 REGB(0x100024) -#define URXH1 REGB(0x104024) -#define UBRDIV0 REGL(0x100028) -#define UBRDIV1 REGL(0x104028) - -/*******************/ -/* SIO Registers */ -/*******************/ - -#define SIOCON REGL(0x114000) -#define SIODAT REGL(0x114004) -#define SBRDR REGL(0x114008) -#define ITVCNT REGL(0x11400c) -#define DCNTZ REGL(0x114010) - -/********************/ -/* IIS Registers */ -/********************/ - -#define IISCON REGL(0x118000) -#define IISMOD REGL(0x118004) -#define IISPSR REGL(0x118008) -#define IISFIFCON REGL(0x11800c) -#define IISFIF REGW(0x118010) - -/**************************/ -/* I/O Ports Registers */ -/**************************/ - -#define PCONA REGL(0x120000) -#define PDATA REGL(0x120004) -#define PCONB REGL(0x120008) -#define PDATB REGL(0x12000c) -#define PCONC REGL(0x120010) -#define PDATC REGL(0x120014) -#define PUPC REGL(0x120018) -#define PCOND REGL(0x12001c) -#define PDATD REGL(0x120020) -#define PUPD REGL(0x120024) -#define PCONE REGL(0x120028) -#define PDATE REGL(0x12002c) -#define PUPE REGL(0x120030) -#define PCONF REGL(0x120034) -#define PDATF REGL(0x120038) -#define PUPF REGL(0x12003c) -#define PCONG REGL(0x120040) -#define PDATG REGL(0x120044) -#define PUPG REGL(0x120048) -#define SPUCR REGL(0x12004c) -#define EXTINT REGL(0x120050) -#define EXTINTPND REGL(0x120054) - -/*********************************/ -/* WatchDog Timers Registers */ -/*********************************/ - -#define WTCON REGL(0x130000) -#define WTDAT REGL(0x130004) -#define WTCNT REGL(0x130008) - -/*********************************/ -/* A/D Converter Registers */ -/*********************************/ - -#define ADCCON REGL(0x140000) -#define ADCPSR REGL(0x140004) -#define ADCDAT REGL(0x140008) - -/***************************/ -/* PWM Timer Registers */ -/***************************/ - -#define TCFG0 REGL(0x150000) -#define TCFG1 REGL(0x150004) -#define TCON REGL(0x150008) -#define TCNTB0 REGL(0x15000c) -#define TCMPB0 REGL(0x150010) -#define TCNTO0 REGL(0x150014) -#define TCNTB1 REGL(0x150018) -#define TCMPB1 REGL(0x15001c) -#define TCNTO1 REGL(0x150020) -#define TCNTB2 REGL(0x150024) -#define TCMPB2 REGL(0x150028) -#define TCNTO2 REGL(0x15002c) -#define TCNTB3 REGL(0x150030) -#define TCMPB3 REGL(0x150034) -#define TCNTO3 REGL(0x150038) -#define TCNTB4 REGL(0x15003c) -#define TCMPB4 REGL(0x150040) -#define TCNTO4 REGL(0x150044) -#define TCNTB5 REGL(0x150048) -#define TCNTO5 REGL(0x15004c) - -/*********************/ -/* IIC Registers */ -/*********************/ - -#define IICCON REGL(0x160000) -#define IICSTAT REGL(0x160004) -#define IICADD REGL(0x160008) -#define IICDS REGL(0x16000c) - -/*********************/ -/* RTC Registers */ -/*********************/ - -#define RTCCON REGB(0x170040) -#define RTCALM REGB(0x170050) -#define ALMSEC REGB(0x170054) -#define ALMMIN REGB(0x170058) -#define ALMHOUR REGB(0x17005c) -#define ALMDAY REGB(0x170060) -#define ALMMON REGB(0x170064) -#define ALMYEAR REGB(0x170068) -#define RTCRST REGB(0x17006c) -#define BCDSEC REGB(0x170070) -#define BCDMIN REGB(0x170074) -#define BCDHOUR REGB(0x170078) -#define BCDDAY REGB(0x17007c) -#define BCDDATE REGB(0x170080) -#define BCDMON REGB(0x170084) -#define BCDYEAR REGB(0x170088) -#define TICINT REGB(0x17008c) - -/*********************************/ -/* Clock & Power Registers */ -/*********************************/ - -#define PLLCON REGL(0x180000) -#define CLKCON REGL(0x180004) -#define CLKSLOW REGL(0x180008) -#define LOCKTIME REGL(0x18000c) - -/**************************************/ -/* Interrupt Controller Registers */ -/**************************************/ - -#define INTCON REGL(0x200000) -#define INTPND REGL(0x200004) -#define INTMOD REGL(0x200008) -#define INTMSK REGL(0x20000c) -#define I_PSLV REGL(0x200010) -#define I_PMST REGL(0x200014) -#define I_CSLV REGL(0x200018) -#define I_CMST REGL(0x20001c) -#define I_ISPR REGL(0x200020) -#define I_ISPC REGL(0x200024) -#define F_ISPR REGL(0x200038) -#define F_ISPC REGL(0x20003c) - -/********************************/ -/* LCD Controller Registers */ -/********************************/ - -#define LCDCON1 REGL(0x300000) -#define LCDCON2 REGL(0x300004) -#define LCDSADDR1 REGL(0x300008) -#define LCDSADDR2 REGL(0x30000c) -#define LCDSADDR3 REGL(0x300010) -#define REDLUT REGL(0x300014) -#define GREENLUT REGL(0x300018) -#define BLUELUT REGL(0x30001c) -#define DP1_2 REGL(0x300020) -#define DP4_7 REGL(0x300024) -#define DP3_5 REGL(0x300028) -#define DP2_3 REGL(0x30002c) -#define DP5_7 REGL(0x300030) -#define DP3_4 REGL(0x300034) -#define DP4_5 REGL(0x300038) -#define DP6_7 REGL(0x30003c) -#define LCDCON3 REGL(0x300040) -#define DITHMODE REGL(0x300044) - -/*********************/ -/* DMA Registers */ -/*********************/ - -#define ZDCON0 REGL(0x280000) -#define ZDISRC0 REGL(0x280004) -#define ZDIDES0 REGL(0x280008) -#define ZDICNT0 REGL(0x28000c) -#define ZDCSRC0 REGL(0x280010) -#define ZDCDES0 REGL(0x280014) -#define ZDCCNT0 REGL(0x280018) - -#define ZDCON1 REGL(0x280020) -#define ZDISRC1 REGL(0x280024) -#define ZDIDES1 REGL(0x280028) -#define ZDICNT1 REGL(0x28002c) -#define ZDCSRC1 REGL(0x280030) -#define ZDCDES1 REGL(0x280034) -#define ZDCCNT1 REGL(0x280038) - -#define BDCON0 REGL(0x380000) -#define BDISRC0 REGL(0x380004) -#define BDIDES0 REGL(0x380008) -#define BDICNT0 REGL(0x38000c) -#define BDCSRC0 REGL(0x380010) -#define BDCDES0 REGL(0x380014) -#define BDCCNT0 REGL(0x380018) - -#define BDCON1 REGL(0x380020) -#define BDISRC1 REGL(0x380024) -#define BDIDES1 REGL(0x380028) -#define BDICNT1 REGL(0x38002c) -#define BDCSRC1 REGL(0x380030) -#define BDCDES1 REGL(0x380034) -#define BDCCNT1 REGL(0x380038) - - -#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) -#define INT_ENABLE(n) INTMSK &= ~(1<<(n)) -#define INT_DISABLE(n) INTMSK |= (1<<(n)) - -#define HARD_RESET_NOW() - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 009863beec..55a4e266a0 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -16,7 +16,7 @@ enum dma_data_direction { static void *dma_alloc_coherent(size_t len, unsigned long *handle) { - *handle = (unsigned long)malloc(len); + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); return (void *)*handle; } diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 79a9597419..e126436093 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -47,6 +47,6 @@ struct arch_global_data { #include <asm-generic/global_data.h> -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 5e2f027ba4..61fee9f06d 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -310,12 +310,6 @@ struct prcm_regs { u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; - u32 prm_sldo_core_setup; - u32 prm_sldo_core_ctrl; - u32 prm_sldo_mpu_setup; - u32 prm_sldo_mpu_ctrl; - u32 prm_sldo_mm_setup; - u32 prm_sldo_mm_ctrl; u32 prm_abbldo_mpu_setup; u32 prm_abbldo_mpu_ctrl; diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 960d12e732..ac54b9359a 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -69,7 +69,7 @@ ENTRY(_main) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ sub sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - mov r8, sp /* GD is above SP */ + mov r9, sp /* GD is above SP */ mov r0, #0 bl board_init_f @@ -81,15 +81,15 @@ ENTRY(_main) * 'here' but relocated. */ - ldr sp, [r8, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ + ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r8, [r8, #GD_BD] /* r8 = gd->bd */ - sub r8, r8, #GD_SIZE /* new GD is below bd */ + ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ + sub r9, r9, #GD_SIZE /* new GD is below bd */ adr lr, here - ldr r0, [r8, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ + ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ add lr, lr, r0 - ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ b relocate_code here: @@ -111,8 +111,8 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ bl red_led_on /* call board_init_r(gd_t *id, ulong dest_addr) */ - mov r0, r8 /* gd_t */ - ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */ + mov r0, r9 /* gd_t */ + ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */ /* call board_init_r */ ldr pc, =board_init_r /* this is auto-relocated! */ diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index ab90430dce..a62a556561 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -22,7 +22,7 @@ ENTRY(relocate_code) ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */ - subs r9, r0, r1 /* r9 <- relocation offset */ + subs r4, r0, r1 /* r4 <- relocation offset */ beq relocate_done /* skip relocation */ ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */ @@ -44,9 +44,9 @@ fixloop: bne fixnext /* relative fix: increase location by offset */ - add r0, r0, r9 + add r0, r0, r4 ldr r1, [r0] - add r1, r1, r9 + add r1, r1, r4 str r1, [r0] fixnext: cmp r2, r3 diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 26d0be47e5..dfcc596815 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -25,9 +25,6 @@ gd_t gdata __attribute__ ((section(".data"))); */ void __weak board_init_f(ulong dummy) { - /* Set the stack pointer. */ - asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile new file mode 100644 index 0000000000..5fcda6e9cc --- /dev/null +++ b/board/armadeus/apf27/Makefile @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2012-2013 +# Eric Jarrige <eric.jarrige@armadeus.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := apf27.o +SOBJS := lowlevel_init.o +ifdef CONFIG_FPGA +COBJS += fpga.o +endif + +SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.S) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c new file mode 100644 index 0000000000..30e720d167 --- /dev/null +++ b/board/armadeus/apf27/apf27.c @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> + * + * based on the files by + * Sascha Hauer, Pengutronix + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <environment.h> +#include <jffs2/jffs2.h> +#include <nand.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/errno.h> +#include "apf27.h" +#include "crc.h" +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Fuse bank 1 row 8 is "reserved for future use" and therefore available for + * customer use. The APF27 board uses this fuse to store the board revision: + * 0: initial board revision + * 1: first revision - Presence of the second RAM chip on the board is blown in + * fuse bank 1 row 9 bit 0 - No hardware change + * N: to be defined + */ +static u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + + return readl(&iim->bank[1].fuse_regs[8]); +} + +/* + * Fuse bank 1 row 9 is "reserved for future use" and therefore available for + * customer use. The APF27 board revision 1 uses the bit 0 to permanently store + * the presence of the second RAM chip + * 0: AFP27 with 1 RAM of 64 MiB + * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB) + */ +static int get_num_ram_bank(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + int nr_dram_banks = 1; + + if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1)) + nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01; + else + nr_dram_banks = CONFIG_NR_DRAM_POPULATED; + + return nr_dram_banks; +} + +static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2, + u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2, + u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr, + u32 puen, u32 gius) +{ + struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE; + + writel(gpio_dr, ®s->port[port].gpio_dr); + writel(ocr1, ®s->port[port].ocr1); + writel(ocr2, ®s->port[port].ocr2); + writel(iconfa1, ®s->port[port].iconfa1); + writel(iconfa2, ®s->port[port].iconfa2); + writel(iconfb1, ®s->port[port].iconfb1); + writel(iconfb2, ®s->port[port].iconfb2); + writel(icr1, ®s->port[port].icr1); + writel(icr2, ®s->port[port].icr2); + writel(imr, ®s->port[port].imr); + writel(gpio_dir, ®s->port[port].gpio_dir); + writel(gpr, ®s->port[port].gpr); + writel(puen, ®s->port[port].puen); + writel(gius, ®s->port[port].gius); +} + +#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \ + ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \ + ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \ + ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \ + ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \ + ACFG_GIUS_##n##_VAL) + +static void apf27_iomux_init(void) +{ + APF27_PORT_INIT(A); + APF27_PORT_INIT(B); + APF27_PORT_INIT(C); + APF27_PORT_INIT(D); + APF27_PORT_INIT(E); + APF27_PORT_INIT(F); +} + +static int apf27_devices_init(void) +{ + int i; + unsigned int mode[] = { + PC5_PF_I2C2_DATA, + PC6_PF_I2C2_CLK, + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +#ifdef CONFIG_MXC_UART + mx27_uart1_init_pins(); +#endif + +#ifdef CONFIG_FEC_MXC + mx27_fec_init_pins(); +#endif + +#ifdef CONFIG_MXC_MMC + mx27_sd2_init_pins(); + imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16)); + gpio_request(PC_PWRON, "pc_pwron"); + gpio_set_value(PC_PWRON, 1); +#endif + return 0; +} + +static void apf27_setup_csx(void) +{ + struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE; + + writel(ACFG_CS0U_VAL, &weim->cs0u); + writel(ACFG_CS0L_VAL, &weim->cs0l); + writel(ACFG_CS0A_VAL, &weim->cs0a); + + writel(ACFG_CS1U_VAL, &weim->cs1u); + writel(ACFG_CS1L_VAL, &weim->cs1l); + writel(ACFG_CS1A_VAL, &weim->cs1a); + + writel(ACFG_CS2U_VAL, &weim->cs2u); + writel(ACFG_CS2L_VAL, &weim->cs2l); + writel(ACFG_CS2A_VAL, &weim->cs2a); + + writel(ACFG_CS3U_VAL, &weim->cs3u); + writel(ACFG_CS3L_VAL, &weim->cs3l); + writel(ACFG_CS3A_VAL, &weim->cs3a); + + writel(ACFG_CS4U_VAL, &weim->cs4u); + writel(ACFG_CS4L_VAL, &weim->cs4l); + writel(ACFG_CS4A_VAL, &weim->cs4a); + + writel(ACFG_CS5U_VAL, &weim->cs5u); + writel(ACFG_CS5L_VAL, &weim->cs5l); + writel(ACFG_CS5A_VAL, &weim->cs5a); + + writel(ACFG_EIM_VAL, &weim->eim); +} + +static void apf27_setup_port(void) +{ + struct system_control_regs *system = + (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; + + writel(ACFG_FMCR_VAL, &system->fmcr); +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + apf27_setup_csx(); + apf27_setup_port(); + apf27_iomux_init(); + apf27_devices_init(); +#if defined(CONFIG_FPGA) + APF27_init_fpga(); +#endif + + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + if (get_num_ram_bank() > 1) + gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + if (get_num_ram_bank() > 1) + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); + else + gd->bd->bi_dram[1].size = 0; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + ulong ramtop; + + if (get_num_ram_bank() > 1) + ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); + else + ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + + return ramtop; +} + +int checkboard(void) +{ + printf("Board: Armadeus APF27 revision %d\n", get_board_rev()); + return 0; +} + +#ifdef CONFIG_SPL_BUILD +inline void hang(void) +{ + for (;;) + ; +} + +void board_init_f(ulong bootflag) +{ + /* + * copy ourselves from where we are running to where we were + * linked at. Use ulong pointers as all addresses involved + * are 4-byte-aligned. + */ + ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; + asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); + asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); + asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); + asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); + for (dst = start_ptr; dst < end_ptr; dst++) + *dst = *(dst+(run_ptr-link_ptr)); + + /* + * branch to nand_boot's link-time address. + */ + asm volatile("ldr pc, =nand_boot"); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h new file mode 100644 index 0000000000..64e7e4dfbb --- /dev/null +++ b/board/armadeus/apf27/apf27.h @@ -0,0 +1,489 @@ +/* + * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __APF27_H +#define __APF27_H + +/* FPGA program pin configuration */ +#define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ +#define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ +#define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ +#define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */ +#define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */ +#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ +#define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ +#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ +#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ +#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ +#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ + +/* MMC pin */ +#define PC_PWRON (GPIO_PORTF | 16) + +/* + * MPU CLOCK source before PLL + * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) + */ +#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ +#define ACFG_MPCTL1_VAL 0 +#define CONFIG_MPLL_FREQ 399 + +#define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ + +/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/ +#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ +#define ACFG_SPCTL1_VAL 0 +#define CONFIG_SPLL_FREQ 300 /* MHz */ + +/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ +#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ + +/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */ +#define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */ + +#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */ +#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ +#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ +#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ +#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */ +#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */ +#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */ +#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */ +#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ +#define CONFIG_CLK0_EN 1 /* CLK0 enabled */ + +/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ +#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */ + +/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ +#define CONFIG_USB_FREQ 60 /* 60 MHz */ + +/* + * SDRAM + */ +#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ +/* micron 64MB */ +#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 + * column address bits + */ +#define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 + * row address bits + */ +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + * 2=4096 3=8192 refresh + */ +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power + * down delay + */ +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read + * cycle delay > 0 + */ +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register + * cycle delay 1..4 + */ +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck + * SDRAM: 0=1ck 1=2ck + */ +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + * refresh to command) + */ +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + * estimated fo CL=1 + * 0=force 3 for lpddr + */ +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + * 3=Eighth 4=Sixteenth + */ +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half + * 2=quater 3=Eighth + */ +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access + * 0 = Burst mode + */ +#endif + +#if (ACFG_SDRAM_MBYTE_SYZE == 128) +/* micron 128MB */ +#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 + * column address bits + */ +#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 + * row address bits + */ +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + * 2=4096 3=8192 refresh + */ +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power + * down delay + */ +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read + * cycle delay > 0 + */ +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register + * cycle delay 1..4 + */ +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck + * SDRAM: 0=1ck 1=2ck + */ +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + * refresh to command) + */ +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + * estimated fo CL=1 + * 0=force 3 for lpddr + */ +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + * 3=Eighth 4=Sixteenth + */ +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half + * 2=quater 3=Eighth + */ +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access + * 0 = Burst mode + */ +#endif + +#if (ACFG_SDRAM_MBYTE_SYZE == 256) +/* micron 256MB */ +#define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 + * column address bits + */ +#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 + * row address bits + */ +#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + * 2=4096 3=8192 refresh + */ +#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power + * down delay + */ +#define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle + * delay > 0 + */ +#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register + * cycle delay 1..4 + */ +#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck + * SDRAM: 0=1ck 1=2ck + */ +#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ +#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ +#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + * refresh to command) + */ +#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + * estimated fo CL=1 + * 0=force 3 for lpddr + */ +#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + * 3=Eighth 4=Sixteenth + */ +#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength + * 1=half + * 2=quater + * 3=Eighth + */ +#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access + * 0 = Burst mode + */ +#endif + +/* + * External interface + */ +/* + * CSCRxU_VAL: + * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 + * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | + * + * 15| x x | x x x x x x | x | x x x x | x x x x |0 + * | CNC | WSC |EW | WWS | EDC | + * + * CSCRxL_VAL: + * 31| x x x x | x x x x | x x x x | x x x x |16 + * | OEA | OEN | EBWA | EBWN | + * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 + * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| + * + * CSCRxA_VAL: + * 31| x x x x | x x x x | x x x x | x x x x |16 + * | EBRA | EBRN | RWA | RWN | + * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 + * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| + */ + +/* CS0 configuration for 16 bit nor flash */ +#define ACFG_CS0U_VAL 0x0000CC03 +#define ACFG_CS0L_VAL 0xa0330D01 +#define ACFG_CS0A_VAL 0x00220800 + +#define ACFG_CS1U_VAL 0x00000f00 +#define ACFG_CS1L_VAL 0x00000D01 +#define ACFG_CS1A_VAL 0 + +#define ACFG_CS2U_VAL 0 +#define ACFG_CS2L_VAL 0 +#define ACFG_CS2A_VAL 0 + +#define ACFG_CS3U_VAL 0 +#define ACFG_CS3L_VAL 0 +#define ACFG_CS3A_VAL 0 + +#define ACFG_CS4U_VAL 0 +#define ACFG_CS4L_VAL 0 +#define ACFG_CS4A_VAL 0 + +/* FPGA 16 bit data bus */ +#define ACFG_CS5U_VAL 0x00000600 +#define ACFG_CS5L_VAL 0x00000D01 +#define ACFG_CS5A_VAL 0 + +#define ACFG_EIM_VAL 0x00002200 + + +/* + * FPGA specific settings + */ + +/* CLKO */ +#define ACFG_CCSR_VAL 0x00000305 +/* drive strength CLKO set to 2 */ +#define ACFG_DSCR10_VAL 0x00020000 +/* drive strength A1..A12 set to 2 */ +#define ACFG_DSCR3_VAL 0x02AAAAA8 +/* drive strength ctrl */ +#define ACFG_DSCR7_VAL 0x00020880 +/* drive strength data */ +#define ACFG_DSCR2_VAL 0xAAAAAAAA + + +/* + * Default configuration for GPIOs and peripherals + */ +#define ACFG_DDIR_A_VAL 0x00000000 +#define ACFG_OCR1_A_VAL 0x00000000 +#define ACFG_OCR2_A_VAL 0x00000000 +#define ACFG_ICFA1_A_VAL 0xFFFFFFFF +#define ACFG_ICFA2_A_VAL 0xFFFFFFFF +#define ACFG_ICFB1_A_VAL 0xFFFFFFFF +#define ACFG_ICFB2_A_VAL 0xFFFFFFFF +#define ACFG_DR_A_VAL 0x00000000 +#define ACFG_GIUS_A_VAL 0xFFFFFFFF +#define ACFG_ICR1_A_VAL 0x00000000 +#define ACFG_ICR2_A_VAL 0x00000000 +#define ACFG_IMR_A_VAL 0x00000000 +#define ACFG_GPR_A_VAL 0x00000000 +#define ACFG_PUEN_A_VAL 0xFFFFFFFF + +#define ACFG_DDIR_B_VAL 0x00000000 +#define ACFG_OCR1_B_VAL 0x00000000 +#define ACFG_OCR2_B_VAL 0x00000000 +#define ACFG_ICFA1_B_VAL 0xFFFFFFFF +#define ACFG_ICFA2_B_VAL 0xFFFFFFFF +#define ACFG_ICFB1_B_VAL 0xFFFFFFFF +#define ACFG_ICFB2_B_VAL 0xFFFFFFFF +#define ACFG_DR_B_VAL 0x00000000 +#define ACFG_GIUS_B_VAL 0xFF3FFFF0 +#define ACFG_ICR1_B_VAL 0x00000000 +#define ACFG_ICR2_B_VAL 0x00000000 +#define ACFG_IMR_B_VAL 0x00000000 +#define ACFG_GPR_B_VAL 0x00000000 +#define ACFG_PUEN_B_VAL 0xFFFFFFFF + +#define ACFG_DDIR_C_VAL 0x00000000 +#define ACFG_OCR1_C_VAL 0x00000000 +#define ACFG_OCR2_C_VAL 0x00000000 +#define ACFG_ICFA1_C_VAL 0xFFFFFFFF +#define ACFG_ICFA2_C_VAL 0xFFFFFFFF +#define ACFG_ICFB1_C_VAL 0xFFFFFFFF +#define ACFG_ICFB2_C_VAL 0xFFFFFFFF +#define ACFG_DR_C_VAL 0x00000000 +#define ACFG_GIUS_C_VAL 0xFFFFC07F +#define ACFG_ICR1_C_VAL 0x00000000 +#define ACFG_ICR2_C_VAL 0x00000000 +#define ACFG_IMR_C_VAL 0x00000000 +#define ACFG_GPR_C_VAL 0x00000000 +#define ACFG_PUEN_C_VAL 0xFFFFFF87 + +#define ACFG_DDIR_D_VAL 0x00000000 +#define ACFG_OCR1_D_VAL 0x00000000 +#define ACFG_OCR2_D_VAL 0x00000000 +#define ACFG_ICFA1_D_VAL 0xFFFFFFFF +#define ACFG_ICFA2_D_VAL 0xFFFFFFFF +#define ACFG_ICFB1_D_VAL 0xFFFFFFFF +#define ACFG_ICFB2_D_VAL 0xFFFFFFFF +#define ACFG_DR_D_VAL 0x00000000 +#define ACFG_GIUS_D_VAL 0xFFFFFFFF +#define ACFG_ICR1_D_VAL 0x00000000 +#define ACFG_ICR2_D_VAL 0x00000000 +#define ACFG_IMR_D_VAL 0x00000000 +#define ACFG_GPR_D_VAL 0x00000000 +#define ACFG_PUEN_D_VAL 0xFFFFFFFF + +#define ACFG_DDIR_E_VAL 0x00000000 +#define ACFG_OCR1_E_VAL 0x00000000 +#define ACFG_OCR2_E_VAL 0x00000000 +#define ACFG_ICFA1_E_VAL 0xFFFFFFFF +#define ACFG_ICFA2_E_VAL 0xFFFFFFFF +#define ACFG_ICFB1_E_VAL 0xFFFFFFFF +#define ACFG_ICFB2_E_VAL 0xFFFFFFFF +#define ACFG_DR_E_VAL 0x00000000 +#define ACFG_GIUS_E_VAL 0xFCFFCCF8 +#define ACFG_ICR1_E_VAL 0x00000000 +#define ACFG_ICR2_E_VAL 0x00000000 +#define ACFG_IMR_E_VAL 0x00000000 +#define ACFG_GPR_E_VAL 0x00000000 +#define ACFG_PUEN_E_VAL 0xFFFFFFFF + +#define ACFG_DDIR_F_VAL 0x00000000 +#define ACFG_OCR1_F_VAL 0x00000000 +#define ACFG_OCR2_F_VAL 0x00000000 +#define ACFG_ICFA1_F_VAL 0xFFFFFFFF +#define ACFG_ICFA2_F_VAL 0xFFFFFFFF +#define ACFG_ICFB1_F_VAL 0xFFFFFFFF +#define ACFG_ICFB2_F_VAL 0xFFFFFFFF +#define ACFG_DR_F_VAL 0x00000000 +#define ACFG_GIUS_F_VAL 0xFF7F8000 +#define ACFG_ICR1_F_VAL 0x00000000 +#define ACFG_ICR2_F_VAL 0x00000000 +#define ACFG_IMR_F_VAL 0x00000000 +#define ACFG_GPR_F_VAL 0x00000000 +#define ACFG_PUEN_F_VAL 0xFFFFFFFF + +/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ +#define ACFG_GPCR_VAL 0x0003000F + +#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN + +/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ +#if (CONFIG_NR_DRAM_BANKS == 1) +#define ACFG_FMCR_VAL 0xFFFFFFF9 +#elif (CONFIG_NR_DRAM_BANKS == 2) +#define ACFG_FMCR_VAL 0xFFFFFFFB +#endif + +#define ACFG_AIPI1_PSR0_VAL 0x20040304 +#define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB +#define ACFG_AIPI2_PSR0_VAL 0x00000000 +#define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF + +/* PCCR enable DMA FEC I2C1 IIM SDHC1 */ +#define ACFG_PCCR0_VAL 0x05070410 +#define ACFG_PCCR1_VAL 0xA14A0608 + +/* + * From here, there should not be any user configuration. + * All Equations are automatic + */ + +/* fixme none integer value (7.5ns) => 2*hclock = 15ns */ +#define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ + +/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ +#define CSCR_MASK 0x0300800D + +#define ACFG_CSCR_VAL \ + (CSCR_MASK \ + |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ + |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ + |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) + +/* SSIx CLKO NFC H264 MSHC */ +#define ACFG_PCDR0_VAL\ + (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ + |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ + |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ + |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ + |(((CONFIG_CLK0_DIV)&0x07)<<22)\ + |(((CONFIG_CLK0_EN)&0x01)<<25)\ + |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) + +/* PERCLKx */ +#define ACFG_PCDR1_VAL\ + (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ + |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ + |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ + |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) + +/* SDRAM controller programming Values */ +#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \ + (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1)) +#define REG_FIELD_SCL_VAL 3 +#define REG_FIELD_SCLIMX_VAL 0 +#else +#define REG_FIELD_SCL_VAL\ + ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH) +#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL +#endif + +#if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH)) +#define REG_FIELD_SRC_VAL 0 +#else +#define REG_FIELD_SRC_VAL\ + ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH) +#endif + +/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ +#define REG_ESDCTL_BASE_CONFIG (0x80020485\ + | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\ + | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\ + | (((ACFG_SDRAM_REFRESH)&0x7)<<13)) + +#define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) +#define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) +#define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) +#define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) + +/* ESDRAMC Configuration Registers : force CL=3 to lpddr */ +#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\ + | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\ + | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\ + | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \ + ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \ + | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ + | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\ + | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \ + | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \ + | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ + | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ + ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \ + | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) + +/* Issue Mode register Command to SDRAM */ +#define ACFG_SDRAM_MODE_REGISTER_VAL\ + ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\ + | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ + | ((0)<<(3)) /* sequentiql access */ \ + /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) + +/* Issue Extended Mode register Command to SDRAM */ +#define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\ + ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\ + | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\ + | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2))) + +/* Issue Precharge all Command to SDRAM */ +#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10) + +#endif /* __APF27_H */ diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c new file mode 100644 index 0000000000..0c08c0640e --- /dev/null +++ b/board/armadeus/apf27/fpga.c @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2002-2013 + * Eric Jarrige <eric.jarrige@armadeus.org> + * + * based on the files by + * Rich Ireland, Enterasys Networks, rireland@enterasys.com + * and + * Keith Outwater, keith_outwater@mvis.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> + +#include <asm/arch/imx-regs.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <command.h> +#include <config.h> +#include "fpga.h" +#include <spartan3.h> +#include "apf27.h" + +/* + * Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * Spartan2 code is used to download our Spartan 3 :) code is compatible. + * Just take care about the file size + */ +Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = { + fpga_pre_fn, + fpga_pgm_fn, + fpga_init_fn, + NULL, + fpga_done_fn, + fpga_clk_fn, + fpga_cs_fn, + fpga_wr_fn, + fpga_rdata_fn, + fpga_wdata_fn, + fpga_busy_fn, + fpga_abort_fn, + fpga_post_fn, +}; + +Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + {Xilinx_Spartan3, + slave_parallel, + 1196128l/8, + (void *)&fpga_fns, + 0, + "3s200aft256"} +}; + +/* + * Initialize GPIO port B before download + */ +int fpga_pre_fn(int cookie) +{ + /* Initialize GPIO pins */ + gpio_set_value(ACFG_FPGA_PWR, 1); + imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO); + gpio_set_value(ACFG_FPGA_RESET, 1); + imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + gpio_set_value(ACFG_FPGA_PRG, 1); + gpio_set_value(ACFG_FPGA_CLK, 1); + gpio_set_value(ACFG_FPGA_RW, 1); + gpio_set_value(ACFG_FPGA_CS, 1); + gpio_set_value(ACFG_FPGA_SUSPEND, 0); + gpio_set_value(ACFG_FPGA_PWR, 0); + udelay(30000); /*wait until supply started*/ + + return cookie; +} + +/* + * Set the FPGA's active-low program line to the specified level + */ +int fpga_pgm_fn(int assert, int flush, int cookie) +{ + debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__, + assert ? "high" : "low"); + gpio_set_value(ACFG_FPGA_PRG, !assert); + return assert; +} + +/* + * Set the FPGA's active-high clock line to the specified level + */ +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__, + assert_clk ? "high" : "low"); + gpio_set_value(ACFG_FPGA_CLK, !assert_clk); + return assert_clk; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int fpga_init_fn(int cookie) +{ + int value; + debug("%s:%d: INIT check... ", __func__, __LINE__); + value = gpio_get_value(ACFG_FPGA_INIT); + /* printf("init value read %x",value); */ +#ifdef CONFIG_SYS_FPGA_IS_PROTO + return value; +#else + return !value; +#endif +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +int fpga_done_fn(int cookie) +{ + debug("%s:%d: DONE check... %s", __func__, __LINE__, + gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low"); + return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL; +} + +/* + * Set the FPGA's wr line to the specified level + */ +int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + debug("%s:%d: FPGA RW... %s ", __func__, __LINE__, + assert_write ? "high" : "low"); + gpio_set_value(ACFG_FPGA_RW, !assert_write); + return assert_write; +} + +int fpga_cs_fn(int assert_cs, int flush, int cookie) +{ + debug("%s:%d: FPGA CS %s ", __func__, __LINE__, + assert_cs ? "high" : "low"); + gpio_set_value(ACFG_FPGA_CS, !assert_cs); + return assert_cs; +} + +int fpga_rdata_fn(unsigned char *data, int cookie) +{ + debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__, + *((char *)ACFG_FPGA_RDATA)); + *data = (unsigned char) + ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF); + return *data; +} + +int fpga_wdata_fn(unsigned char data, int flush, int cookie) +{ + debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__, + data); + *((unsigned short *)ACFG_FPGA_WDATA) = data; + return data; +} + +int fpga_abort_fn(int cookie) +{ + return fpga_post_fn(cookie); +} + + +int fpga_busy_fn(int cookie) +{ + return 1; +} + +int fpga_post_fn(int cookie) +{ + debug("%s:%d: FPGA POST ", __func__, __LINE__); + + imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN); + imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN); + imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN); + gpio_set_value(ACFG_FPGA_PRG, 1); + gpio_set_value(ACFG_FPGA_RESET, 0); + imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + return cookie; +} + +void apf27_fpga_setup(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + struct system_control_regs *system = + (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; + + /* Configure FPGA CLKO */ + writel(ACFG_CCSR_VAL, &pll->ccsr); + + /* Configure strentgh for FPGA */ + writel(ACFG_DSCR10_VAL, &system->dscr10); + writel(ACFG_DSCR3_VAL, &system->dscr3); + writel(ACFG_DSCR7_VAL, &system->dscr7); + writel(ACFG_DSCR2_VAL, &system->dscr2); +} + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +void APF27_init_fpga(void) +{ + int i; + + apf27_fpga_setup(); + + fpga_init(); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i); + fpga_add(fpga_xilinx, &fpga[i]); + } + + return; +} diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h new file mode 100644 index 0000000000..84a5244a6d --- /dev/null +++ b/board/armadeus/apf27/fpga.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2002-2013 + * Eric Jarrige <eric.jarrige@armadeus.org> + * + * based on the files by + * Rich Ireland, Enterasys Networks, rireland@enterasys.com + * and + * Keith Outwater, keith_outwater@mvis.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +extern void APF27_init_fpga(void); + +extern int fpga_pre_fn(int cookie); +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_cs_fn(int assert_cs, int flush, int cookie); +extern int fpga_init_fn(int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(int assert_write, int flush, int cookie); +extern int fpga_rdata_fn(unsigned char *data, int cookie); +extern int fpga_wdata_fn(unsigned char data, int flush, int cookie); +extern int fpga_abort_fn(int cookie); +extern int fpga_post_fn(int cookie); +extern int fpga_busy_fn(int cookie); diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S new file mode 100644 index 0000000000..4293cb1080 --- /dev/null +++ b/board/armadeus/apf27/lowlevel_init.S @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <generated/asm-offsets.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/arch/imx-regs.h> +#include "apf27.h" + + .macro init_aipi + /* + * setup AIPI1 and AIPI2 + */ + write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL + write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL + write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL + write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL + + /* Change SDRAM signal strengh */ + ldr r0, =GPCR + ldr r1, =ACFG_GPCR_VAL + ldr r5, [r0] + orr r5, r5, r1 + str r5, [r0] + + .endm /* init_aipi */ + + .macro init_clock + ldr r0, =CSCR + /* disable MPLL/SPLL first */ + ldr r1, [r0] + bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) + str r1, [r0] + + /* + * pll clock initialization predefined in apf27.h + */ + write32 MPCTL0, ACFG_MPCTL0_VAL + write32 SPCTL0, ACFG_SPCTL0_VAL + + write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART + + /* + * add some delay here + */ + mov r1, #0x1000 + 1: subs r1, r1, #0x1 + bne 1b + + /* peripheral clock divider */ + write32 PCDR0, ACFG_PCDR0_VAL + write32 PCDR1, ACFG_PCDR1_VAL + + /* Configure PCCR0 and PCCR1 */ + write32 PCCR0, ACFG_PCCR0_VAL + write32 PCCR1, ACFG_PCCR1_VAL + + .endm /* init_clock */ + + .macro init_ddr + /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ + ldr r0, =IMX_ESD_BASE + ldr r4, =ESDMISC_SDRAM_RDY +2: ldr r1, [r0, #ESDMISC_ROF] + ands r1, r1, r4 + bpl 2b + + /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ + ldr r0, =IMX_ESD_BASE + ldr r4, =ACFG_ESDMISC_VAL + orr r1, r4, #ESDMISC_MDDR_DL_RST + str r1, [r0, #ESDMISC_ROF] + + /* Hold for more than 200ns */ + ldr r1, =0x10000 +1: subs r1, r1, #0x1 + bne 1b + + str r4, [r0] + + ldr r0, =IMX_ESD_BASE + ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL + str r1, [r0, #ESDCFG0_ROF] + + ldr r0, =IMX_ESD_BASE + ldr r1, =ACFG_PRECHARGE_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* write8(0xA0001000, any value) */ + ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL + strb r2, [r1] + + ldr r1, =ACFG_AUTOREFRESH_CMD + str r1, [r0, #ESDCTL0_ROF] + + ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ + + ldr r6,=0x7 /* load loop counter */ +1: str r5,[r4] /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 + bne 1b + + ldr r1, =ACFG_SET_MODE_REG_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* set standard mode register */ + ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL + strb r2, [r4] + + /* set extended mode register */ + ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL + strb r5, [r4] + + ldr r1, =ACFG_NORMAL_RW_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* 2nd sdram */ + ldr r0, =IMX_ESD_BASE + ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL + str r1, [r0, #ESDCFG1_ROF] + + ldr r0, =IMX_ESD_BASE + ldr r1, =ACFG_PRECHARGE_CMD + str r1, [r0, #ESDCTL1_ROF] + + /* write8(0xB0001000, any value) */ + ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL + strb r2, [r1] + + ldr r1, =ACFG_AUTOREFRESH_CMD + str r1, [r0, #ESDCTL1_ROF] + + ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ + + ldr r6,=0x7 /* load loop counter */ +1: str r5,[r4] /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 + bne 1b + + ldr r1, =ACFG_SET_MODE_REG_CMD + str r1, [r0, #ESDCTL1_ROF] + + /* set standard mode register */ + ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL + strb r2, [r4] + + /* set extended mode register */ + ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL + strb r2, [r4] + + ldr r1, =ACFG_NORMAL_RW_CMD + str r1, [r0, #ESDCTL1_ROF] + .endm /* init_ddr */ + +.globl lowlevel_init +lowlevel_init: + + init_aipi + init_clock +#ifdef CONFIG_SPL_BUILD + init_ddr +#endif + + mov pc, lr diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c index 3b05baaa70..81419f9635 100644 --- a/board/bluegiga/apx4devkit/spl_boot.c +++ b/board/bluegiga/apx4devkit/spl_boot.c @@ -132,9 +132,9 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, }; -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); /* switch LED on */ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index f664f6de6b..2b61e5d2a9 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -593,6 +593,7 @@ int board_video_skip(void) if (!panel) { panel = displays[0].mode.name; printf("No panel detected: default to %s\n", panel); + i = 0; } } else { for (i = 0; i < ARRAY_SIZE(displays); i++) { @@ -609,9 +610,10 @@ int board_video_skip(void) displays[i].mode.name, displays[i].mode.xres, displays[i].mode.yres); - } else + } else { printf("LCD %s cannot be configured: %d\n", displays[i].mode.name, ret); + } } else { printf("unsupported panel %s\n", panel); ret = -EINVAL; diff --git a/arch/arm/cpu/s3c44b0/Makefile b/board/creative/xfi3/Makefile index 39fdbf86c9..4dc2b48053 100644 --- a/arch/arm/cpu/s3c44b0/Makefile +++ b/board/creative/xfi3/Makefile @@ -7,21 +7,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).o +LIB = $(obj)lib$(BOARD).o -START = start.o +ifndef CONFIG_SPL_BUILD +COBJS := xfi3.o +else +COBJS := spl_boot.o +endif -COBJS += cache.o -COBJS += cpu.o -COBJS += timer.o +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/creative/xfi3/spl_boot.c b/board/creative/xfi3/spl_boot.c new file mode 100644 index 0000000000..af7aa0ebdd --- /dev/null +++ b/board/creative/xfi3/spl_boot.c @@ -0,0 +1,134 @@ +/* + * Creative ZEN X-Fi3 setup + * + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx23.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* EMI */ + MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, + + MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + + MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, + MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, + MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + + MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP, + + MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP, + MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP, + + /* PWM -- FIXME */ + MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP, +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* mDDR configuration values */ + const uint32_t regs[] = { + 0x01010001, 0x00010000, 0x01000000, 0x00000001, + 0x00010101, 0x00000001, 0x00010000, 0x01000001, + 0x01010000, 0x00000001, 0x07000200, 0x04070203, + 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, + 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, + 0x03061323, 0x0000000a, 0x00080008, 0x00200020, + 0x00200020, 0x00200020, 0x000003f7, 0x00000000, + 0x00000000, 0x00000000, 0x00000020, 0x00000000, + 0x001023cd, 0x20410010, 0x00006665, 0x00000000, + 0x00000101, 0x00000001, 0x00000000, 0x00000000, + }; + memcpy(dram_vals, regs, sizeof(regs)); +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/creative/xfi3/xfi3.c b/board/creative/xfi3/xfi3.c new file mode 100644 index 0000000000..1d83ea89aa --- /dev/null +++ b/board/creative/xfi3/xfi3.c @@ -0,0 +1,224 @@ +/* + * Creative ZEN X-Fi3 board + * + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * Hardware investigation done by: + * + * Amaury Pouly <amaury.pouly@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx23.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#ifdef CONFIG_CMD_MMC +static int xfi3_mmc_cd(int id) +{ + switch (id) { + case 0: + /* The SSP_DETECT is inverted on this board. */ + return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1); + case 1: + /* Phison bridge always present */ + return 1; + default: + return 0; + } +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* MicroSD slot */ + gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1); + gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0); + ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd); + if (ret) + return ret; + + /* Phison SD-NAND bridge */ + ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd); + + return ret; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static int mxsfb_write_byte(uint32_t payload, const unsigned int data) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + const unsigned int timeout = 0x10000; + + if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, + timeout)) + return -ETIMEDOUT; + + writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | + (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET), + ®s->hw_lcdif_transfer_count); + + writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN, + ®s->hw_lcdif_ctrl_clr); + + if (data) + writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set); + + writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); + + if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, + timeout)) + return -ETIMEDOUT; + + writel(payload, ®s->hw_lcdif_data); + return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, + timeout); +} + +static void mxsfb_write_register(uint32_t reg, uint32_t data) +{ + mxsfb_write_byte(reg, 0); + mxsfb_write_byte(data, 1); +} + +static const struct { + uint8_t reg; + uint8_t delay; + uint16_t val; +} lcd_regs[] = { + { 0x01, 0, 0x001c }, + { 0x02, 0, 0x0100 }, + /* Writing 0x30 to reg. 0x03 flips the LCD */ + { 0x03, 0, 0x1038 }, + { 0x08, 0, 0x0808 }, + /* This can contain 0x111 to rotate the LCD. */ + { 0x0c, 0, 0x0000 }, + { 0x0f, 0, 0x0c01 }, + { 0x20, 0, 0x0000 }, + { 0x21, 30, 0x0000 }, + /* Wait 30 mS here */ + { 0x10, 0, 0x0a00 }, + { 0x11, 30, 0x1038 }, + /* Wait 30 mS here */ + { 0x12, 0, 0x1010 }, + { 0x13, 0, 0x0050 }, + { 0x14, 0, 0x4f58 }, + { 0x30, 0, 0x0000 }, + { 0x31, 0, 0x00db }, + { 0x32, 0, 0x0000 }, + { 0x33, 0, 0x0000 }, + { 0x34, 0, 0x00db }, + { 0x35, 0, 0x0000 }, + { 0x36, 0, 0x00af }, + { 0x37, 0, 0x0000 }, + { 0x38, 0, 0x00db }, + { 0x39, 0, 0x0000 }, + { 0x50, 0, 0x0000 }, + { 0x51, 0, 0x0705 }, + { 0x52, 0, 0x0e0a }, + { 0x53, 0, 0x0300 }, + { 0x54, 0, 0x0a0e }, + { 0x55, 0, 0x0507 }, + { 0x56, 0, 0x0000 }, + { 0x57, 0, 0x0003 }, + { 0x58, 0, 0x090a }, + { 0x59, 30, 0x0a09 }, + /* Wait 30 mS here */ + { 0x07, 30, 0x1017 }, + /* Wait 40 mS here */ + { 0x36, 0, 0x00af }, + { 0x37, 0, 0x0000 }, + { 0x38, 0, 0x00db }, + { 0x39, 0, 0x0000 }, + { 0x20, 0, 0x0000 }, + { 0x21, 0, 0x0000 }, +}; + +void board_mxsfb_system_setup(void) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + int i; + + /* Switch the LCDIF into System-Mode */ + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE | + LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr); + + /* Restart the SmartLCD controller */ + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_set); + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_clr); + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_set); + mdelay(50); + + /* Program the SmartLCD controller */ + writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set); + + writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) | + (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) | + (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) | + (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET), + ®s->hw_lcdif_timing); + + /* + * OTM2201A init and configuration sequence. + */ + for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) { + mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val); + if (lcd_regs[i].delay) + mdelay(lcd_regs[i].delay); + } + /* Turn on Framebuffer Upload Mode */ + mxsfb_write_byte(0x22, 0); + + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT, + ®s->hw_lcdif_ctrl_set); +} +#endif + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* Turn on PWM backlight */ + gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + usb_eth_initialize(bis); + return 0; +} diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index f4453d64ab..33d38cfc54 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -116,6 +116,8 @@ int board_eth_init(bd_t *bis) int ret; ret = cpu_eth_init(bis); + if (ret) + return ret; clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c index 525ba6ae75..5a1010e595 100644 --- a/board/denx/m28evk/spl_boot.c +++ b/board/denx/m28evk/spl_boot.c @@ -200,7 +200,7 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), }; -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index 054ca0a93b..603f4dcfd1 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -129,7 +129,7 @@ void mxs_adjust_memory_params(uint32_t *dram_vals) dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG; } -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 6ca842ba86..97c2376da1 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -200,7 +200,7 @@ void mxs_adjust_memory_params(uint32_t *dram_vals) dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; } -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index a307f27ef5..5005fe23dd 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -103,10 +103,12 @@ int board_eth_init(bd_t *bis) int ret; ret = cpu_eth_init(bis); + if (ret) + return ret; /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, - &clkctrl_regs->hw_clkctrl_enet); + &clkctrl_regs->hw_clkctrl_enet); /* Power-on FECs */ gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 427c83a8ff..9fabef5af5 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -251,14 +251,12 @@ int board_late_init(void) int board_eth_init(bd_t *bis) { - int rc = -ENODEV; #if defined(CONFIG_SMC911X) - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + if (rc) + return rc; #endif - - cpu_eth_init(bis); - - return rc; + return cpu_eth_init(bis); } #if defined(CONFIG_FSL_ESDHC) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 1cdf2cb097..c55ee8783d 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -200,7 +200,7 @@ int board_eth_init(bd_t *bis) if (ret) printf("FEC MXC: %s:failed\n", __func__); - return 0; + return ret; } #define BOARD_REV_B 0x200 diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 5db516d5fd..9dbe605cf4 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -234,47 +234,172 @@ int board_phy_config(struct phy_device *phydev) } #if defined(CONFIG_VIDEO_IPUV3) -static struct fb_videomode const hdmi = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; }; -int board_video_skip(void) +static int detect_hdmi(struct display_info_t const *dev) { - int ret; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; +} - ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} - if (ret) - printf("HDMI cannot be configured: %d\n", ret); +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT; + writel(reg, &iomux->gpr[2]); +} +static struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; - imx_enable_hdmi_phy(); - return ret; +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect && dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; } static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; int reg; enable_ipu_clock(); imx_setup_hdmi(); + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + reg = readl(&mxc_ccm->chsccdr); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK + | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -297,7 +422,7 @@ int board_eth_init(bd_t *bis) if (ret) printf("FEC MXC: %s:failed\n", __func__); - return 0; + return ret; } int board_early_init_f(void) diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 5b6ef81a4b..643fdac2b3 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -18,6 +18,7 @@ #include <common.h> #include <fsl_esdhc.h> #include <mmc.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -29,6 +30,12 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ETH_PHY_RESET IMX_GPIO_NR(4, 21) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -50,11 +57,35 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +static iomux_v3_cfg_t const fec_pads[] = { + MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); + + /* Reset LAN8720 PHY */ + gpio_direction_output(ETH_PHY_RESET , 0); + udelay(1000); + gpio_set_value(ETH_PHY_RESET, 1); +} + static struct fsl_esdhc_cfg usdhc_cfg[1] = { {USDHC2_BASE_ADDR}, }; @@ -72,6 +103,40 @@ int board_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(); + + ret = cpu_eth_init(bis); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + return ret; + } + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_base_regs *iomuxc_regs = + (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + int ret; + + /* clear gpr1[14], gpr1[18:17] to select anatop clock */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); + + ret = enable_fec_anatop_clock(); + if (ret) + return ret; + + return 0; +} +#endif + + int board_early_init_f(void) { setup_iomux_uart(); @@ -83,6 +148,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif return 0; } diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 0a6630395d..5272dfa4e6 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -85,7 +85,7 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), }; -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } diff --git a/board/sandisk/sansa_fuze_plus/Makefile b/board/sandisk/sansa_fuze_plus/Makefile new file mode 100644 index 0000000000..571cc077fa --- /dev/null +++ b/board/sandisk/sansa_fuze_plus/Makefile @@ -0,0 +1,31 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifndef CONFIG_SPL_BUILD +COBJS := sfp.o +else +COBJS := spl_boot.o +endif + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sandisk/sansa_fuze_plus/sfp.c b/board/sandisk/sansa_fuze_plus/sfp.c new file mode 100644 index 0000000000..a3865ad56a --- /dev/null +++ b/board/sandisk/sansa_fuze_plus/sfp.c @@ -0,0 +1,388 @@ +/* + * SanDisk Sansa Fuze Plus board + * + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * Hardware investigation done by: + * + * Amaury Pouly <amaury.pouly@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx23.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#ifdef CONFIG_CMD_MMC +static int xfi3_mmc_cd(int id) +{ + switch (id) { + case 0: + /* The SSP_DETECT is inverted on this board. */ + return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1); + case 1: + /* Internal eMMC always present */ + return 1; + default: + return 0; + } +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* MicroSD slot */ + gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1); + gpio_direction_output(MX23_PAD_GPMI_D08__GPIO_0_8, 0); + ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd); + if (ret) + return ret; + + /* Internal eMMC */ + gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0); + ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd); + + return ret; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +const iomux_cfg_t iomux_lcd_gpio[] = { + MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__GPIO_1_6 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__GPIO_1_7 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__GPIO_1_8 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__GPIO_1_9 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__GPIO_1_10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__GPIO_1_11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__GPIO_1_12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__GPIO_1_13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__GPIO_1_14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__GPIO_1_15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RS__GPIO_1_19 | MUX_CONFIG_LCD, + MX23_PAD_LCD_WR__GPIO_1_20 | MUX_CONFIG_LCD, + MX23_PAD_LCD_CS__GPIO_1_21 | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__GPIO_1_23 | MUX_CONFIG_LCD, +}; + +const iomux_cfg_t iomux_lcd_lcd[] = { + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, + MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, + MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, +}; + +static int mxsfb_read_register(uint32_t reg, uint32_t *value) +{ + iomux_cfg_t mux; + uint32_t val = 0; + int i; + + /* Mangle the register offset. */ + reg = ((reg & 0xff) << 1) | (((reg >> 8) & 0xff) << 10); + + /* + * The SmartLCD interface on MX233 can only do WRITE operation + * via the LCDIF controller. Implement the READ operation by + * fiddling with bits. + */ + mxs_iomux_setup_multiple_pads(iomux_lcd_gpio, + ARRAY_SIZE(iomux_lcd_gpio)); + + gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1); + gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1); + gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1); + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); + + for (i = 0; i < 18; i++) { + mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); + gpio_direction_output(mux, 0); + } + + udelay(2); + gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 0); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 0); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 0); + udelay(1); + + for (i = 0; i < 18; i++) { + mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); + gpio_direction_output(mux, (reg >> i) & 1); + } + udelay(1); + + gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1); + udelay(3); + + for (i = 0; i < 18; i++) { + mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); + gpio_direction_input(mux); + } + udelay(2); + + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); + udelay(3); + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0); + udelay(2); + + for (i = 0; i < 18; i++) { + mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO); + val |= !!gpio_get_value(mux) << i; + } + udelay(1); + + gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1); + udelay(1); + gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1); + udelay(1); + + mxs_iomux_setup_multiple_pads(iomux_lcd_lcd, + ARRAY_SIZE(iomux_lcd_lcd)); + + /* Demangle the register value. */ + *value = ((val >> 1) & 0xff) | ((val >> 2) & 0xff00); + + writel(val, 0x2000); + return 0; +} + +static int mxsfb_write_byte(uint32_t payload, const unsigned int data) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + const unsigned int timeout = 0x10000; + + /* What is going on here I do not know. FIXME */ + payload = ((payload & 0xff) << 1) | (((payload >> 8) & 0xff) << 10); + + if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, + timeout)) + return -ETIMEDOUT; + + writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | + (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET), + ®s->hw_lcdif_transfer_count); + + writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN, + ®s->hw_lcdif_ctrl_clr); + + if (data) + writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set); + + writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); + + if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, + timeout)) + return -ETIMEDOUT; + + writel(payload, ®s->hw_lcdif_data); + return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, + timeout); +} + +static void mxsfb_write_register(uint32_t reg, uint32_t data) +{ + mxsfb_write_byte(reg, 0); + mxsfb_write_byte(data, 1); +} + +static const struct { + uint8_t reg; + uint8_t delay; + uint16_t val; +} lcd_regs[] = { + { 0xe5, 0 , 0x78f0 }, + { 0xe3, 0 , 0x3008 }, + { 0xe7, 0 , 0x0012 }, + { 0xef, 0 , 0x1231 }, + { 0x00, 0 , 0x0001 }, + { 0x01, 0 , 0x0100 }, + { 0x02, 0 , 0x0700 }, + { 0x03, 0 , 0x1030 }, + { 0x04, 0 , 0x0000 }, + { 0x08, 0 , 0x0207 }, + { 0x09, 0 , 0x0000 }, + { 0x0a, 0 , 0x0000 }, + { 0x0c, 0 , 0x0000 }, + { 0x0d, 0 , 0x0000 }, + { 0x0f, 0 , 0x0000 }, + { 0x10, 0 , 0x0000 }, + { 0x11, 0 , 0x0007 }, + { 0x12, 0 , 0x0000 }, + { 0x13, 20 , 0x0000 }, + /* Wait 20 mS here. */ + { 0x10, 0 , 0x1290 }, + { 0x11, 50 , 0x0007 }, + /* Wait 50 mS here. */ + { 0x12, 50 , 0x0019 }, + /* Wait 50 mS here. */ + { 0x13, 0 , 0x1700 }, + { 0x29, 50 , 0x0014 }, + /* Wait 50 mS here. */ + { 0x20, 0 , 0x0000 }, + { 0x21, 0 , 0x0000 }, + { 0x30, 0 , 0x0504 }, + { 0x31, 0 , 0x0007 }, + { 0x32, 0 , 0x0006 }, + { 0x35, 0 , 0x0106 }, + { 0x36, 0 , 0x0202 }, + { 0x37, 0 , 0x0504 }, + { 0x38, 0 , 0x0500 }, + { 0x39, 0 , 0x0706 }, + { 0x3c, 0 , 0x0204 }, + { 0x3d, 0 , 0x0202 }, + { 0x50, 0 , 0x0000 }, + { 0x51, 0 , 0x00ef }, + { 0x52, 0 , 0x0000 }, + { 0x53, 0 , 0x013f }, + { 0x60, 0 , 0xa700 }, + { 0x61, 0 , 0x0001 }, + { 0x6a, 0 , 0x0000 }, + { 0x2b, 50 , 0x000d }, + /* Wait 50 mS here. */ + { 0x90, 0 , 0x0011 }, + { 0x92, 0 , 0x0600 }, + { 0x93, 0 , 0x0003 }, + { 0x95, 0 , 0x0110 }, + { 0x97, 0 , 0x0000 }, + { 0x98, 0 , 0x0000 }, + { 0x07, 0 , 0x0173 }, +}; + +void board_mxsfb_system_setup(void) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + uint32_t id; + int i; + + /* Switch the LCDIF into System-Mode */ + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE | + LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr); + + /* To program the LCD, switch to 18bit bus + 18bit data. */ + clrsetbits_le32(®s->hw_lcdif_ctrl, + LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK, + LCDIF_CTRL_WORD_LENGTH_18BIT | + LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT); + + mxsfb_read_register(0, &id); + writel(id, 0x2004); + + /* Restart the SmartLCD controller */ + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_set); + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_clr); + mdelay(50); + writel(1, ®s->hw_lcdif_ctrl1_set); + mdelay(50); + + /* Program the SmartLCD controller */ + writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set); + + writel((0x02 << LCDIF_TIMING_CMD_HOLD_OFFSET) | + (0x02 << LCDIF_TIMING_CMD_SETUP_OFFSET) | + (0x02 << LCDIF_TIMING_DATA_HOLD_OFFSET) | + (0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET), + ®s->hw_lcdif_timing); + + /* + * ILI9325 init and configuration sequence. + */ + for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) { + mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val); + if (lcd_regs[i].delay) + mdelay(lcd_regs[i].delay); + } + /* Turn on Framebuffer Upload Mode */ + mxsfb_write_byte(0x22, 0); + + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT, + ®s->hw_lcdif_ctrl_set); + + /* Operate the framebuffer in 16bit mode. */ + clrsetbits_le32(®s->hw_lcdif_ctrl, + LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK, + LCDIF_CTRL_WORD_LENGTH_16BIT | + LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT); +} +#endif + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* Turn on PWM backlight */ + gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + usb_eth_initialize(bis); + return 0; +} diff --git a/board/sandisk/sansa_fuze_plus/spl_boot.c b/board/sandisk/sansa_fuze_plus/spl_boot.c new file mode 100644 index 0000000000..825be829c7 --- /dev/null +++ b/board/sandisk/sansa_fuze_plus/spl_boot.c @@ -0,0 +1,140 @@ +/* + * SanDisk Sansa Fuze Plus setup + * + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx23.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* EMI */ + MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, + + MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + + MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD, + MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD, + MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + + MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, + MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D08__GPIO_0_8 | MUX_CONFIG_SSP, + + MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D04__SSP2_DATA4 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D05__SSP2_DATA5 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D06__SSP2_DATA6 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_D07__SSP2_DATA7 | MUX_CONFIG_SSP, + MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP, + MX23_PAD_GPMI_WRN__SSP2_SCK | + (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL), + MX23_PAD_PWM3__GPIO_1_29 | MUX_CONFIG_SSP, + + /* PWM -- FIXME */ + MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP, +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* mDDR configuration values */ + const uint32_t regs[] = { + 0x01010001, 0x00010000, 0x01000000, 0x00000001, + 0x00010101, 0x00000001, 0x00010000, 0x01000001, + 0x01010000, 0x00000001, 0x07000200, 0x04070203, + 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, + 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, + 0x03061323, 0x0000000a, 0x00080008, 0x00200020, + 0x00200020, 0x00200020, 0x000003f7, 0x00000000, + 0x00000000, 0x00000000, 0x00000020, 0x00000000, + 0x001023cd, 0x20410010, 0x00006665, 0x00000000, + 0x00000101, 0x00000001, 0x00000000, 0x00000000, + }; + memcpy(dram_vals, regs, sizeof(regs)); +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/schulercontrol/sc_sps_1/spl_boot.c b/board/schulercontrol/sc_sps_1/spl_boot.c index 1fe9224e5a..60195c3a7d 100644 --- a/board/schulercontrol/sc_sps_1/spl_boot.c +++ b/board/schulercontrol/sc_sps_1/spl_boot.c @@ -138,9 +138,9 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED, }; -void board_init_ll(void) +void board_init_ll(const uint32_t arg, const uint32_t *resptr) { - mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } void mxs_adjust_memory_params(uint32_t *dram_vals) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index cc0442612f..c2fc5a613b 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -26,6 +26,8 @@ #include <i2c.h> #include <miiphy.h> #include <cpsw.h> +#include <power/tps65217.h> +#include <power/tps65910.h> #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -244,6 +246,150 @@ const struct dpll_params dpll_ddr_evm_sk = { const struct dpll_params dpll_ddr_bone_black = { 400, OSC-1, 1, -1, -1, -1, -1}; +void am33xx_spl_board_init(void) +{ + struct am335x_baseboard_id header; + int mpu_vdd; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + if (board_is_bone(&header) || board_is_bone_lt(&header)) { + /* BeagleBone PMIC Code */ + int usb_cur_lim; + + /* + * Only perform PMIC configurations if board rev > A1 + * on Beaglebone White + */ + if (board_is_bone(&header) && !strncmp(header.version, + "00A1", 4)) + return; + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * On Beaglebone White we need to ensure we have AC power + * before increasing the frequency. + */ + if (board_is_bone(&header)) { + uchar pmic_status_reg; + if (tps65217_reg_read(TPS65217_STATUS, + &pmic_status_reg)) + return; + if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { + puts("No AC power, disabling frequency switch\n"); + return; + } + } + + /* + * Override what we have detected since we know if we have + * a Beaglebone Black it supports 1GHz. + */ + if (board_is_bone_lt(&header)) + dpll_mpu_opp100.m = MPUPLL_M_1000; + + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_POWER_PATH, + usb_cur_lim, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* + * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. + * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. + */ + if (board_is_bone(&header)) { + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } else { + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } else { + int sil_rev; + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) + return; + + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, + dpll_mpu_opp100.m); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) + return; + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + } + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + const struct dpll_params *get_dpll_ddr_params(void) { struct am335x_baseboard_id header; diff --git a/boards.cfg b/boards.cfg index 9fc77fb4da..c90ddddf13 100644 --- a/boards.cfg +++ b/boards.cfg @@ -196,15 +196,18 @@ Active arm arm926ejs mb86r0x syteco jadecpu Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com> Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com> Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de> +Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org> Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de> Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de> Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit apx4devkit Lauri Hintsala <lauri.hintsala@bluegiga.com> +Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut <marek.vasut@gmail.com> Active arm arm926ejs mxs denx m28evk m28evk m28evk Marek Vasut <marek.vasut@gmail.com> Active arm arm926ejs mxs freescale mx23evk mx23evk mx23evk Otavio Salvador <otavio@ossystems.com.br> Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com> Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com> Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com> Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com> +Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com> Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com> Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it> Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it> diff --git a/doc/README.mxs b/doc/README.mxs index 5d9e72f958..2919bbfee1 100644 --- a/doc/README.mxs +++ b/doc/README.mxs @@ -63,6 +63,11 @@ copy the binary by hand: Make sure the "elftosb" binary can be found in your $PATH, in this case this means "/usr/local/bin/" has to be in your $PATH. +Install the 'libssl-dev' package as well. On a Debian-based distribution, this +package can be installed as follows: + + $ sudo apt-get install libssl-dev + 2) Compiling U-Boot for a MXS based board ------------------------------------------- diff --git a/doc/driver-model/UDM-rtc.txt b/doc/driver-model/UDM-rtc.txt index 5d9fb333ba..6aaeb86f27 100644 --- a/doc/driver-model/UDM-rtc.txt +++ b/doc/driver-model/UDM-rtc.txt @@ -228,31 +228,26 @@ III) Analysis of in-tree drivers The driver is standard rtc. Simple conversion is possible. - 34) drivers/rtc/s3c44b0_rtc.c - ----------------------------- - The driver is standard rtc. Simple conversion is possible. - - - 35) drivers/rtc/ds1337.c + 34) drivers/rtc/ds1337.c ------------------------ The driver is standard rtc. Simple conversion is possible. - 36) drivers/rtc/isl1208.c + 35) drivers/rtc/isl1208.c ------------------------- The driver is standard rtc. Simple conversion is possible. - 37) drivers/rtc/max6900.c + 36) drivers/rtc/max6900.c ------------------------- The driver is standard rtc. Simple conversion is possible. - 38) drivers/rtc/mc146818.c + 37) drivers/rtc/mc146818.c -------------------------- The driver is standard rtc. Simple conversion is possible. - 39) drivers/rtc/at91sam9_rtt.c + 38) drivers/rtc/at91sam9_rtt.c ------------------------------ The driver is standard rtc. Simple conversion is possible. diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt index 1011c32d18..54f853e0e4 100644 --- a/doc/driver-model/UDM-serial.txt +++ b/doc/driver-model/UDM-serial.txt @@ -148,32 +148,28 @@ III) Analysis of in-tree drivers -------------------- This driver, being quite ad-hoc might need some work to bring back to shape. - 22) serial_s3c44b0.c - -------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 23) serial_s5p.c + 22) serial_s5p.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 24) serial_sa1100.c + 23) serial_sa1100.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 25) serial_sh.c + 24) serial_sh.c --------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 26) serial_xuartlite.c + 25) serial_xuartlite.c ---------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 27) usbtty.c + 26) usbtty.c ------------ This driver seems very complicated and entangled with USB framework. The conversion might be complicated here. - 28) arch/powerpc/cpu/mpc512x/serial.c + 27) arch/powerpc/cpu/mpc512x/serial.c ------------------------------------- This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to proper place. diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 37ccbd1423..df3092eaf0 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -21,7 +21,6 @@ COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o -COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o COBJS-$(CONFIG_SH_I2C) += sh_i2c.o diff --git a/drivers/i2c/s3c44b0_i2c.c b/drivers/i2c/s3c44b0_i2c.c deleted file mode 100644 index 8445e01caf..0000000000 --- a/drivers/i2c/s3c44b0_i2c.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/hardware.h> - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr) -{ - /* - setting up I2C support - */ - unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; - - save_F = PCONF; - save_PF = PUPF; - - rPCONF = ((save_F & ~(0xF))| 0xa); - rPUPF = (save_PF | 0x3); - PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ - PUPF = rPUPF; /* Disable pull-up */ - - /* Configuring pin for WC pin of EEprom */ - rPCONA = PCONA; - rPCONA &= ~(1<<9); - PCONA = rPCONA; - - rPDATA = PDATA; - rPDATA &= ~(1<<9); - PDATA = rPDATA; - - /* - Enable ACK, IICCLK=MCLK/16, enable interrupt - 75MHz/16/(12+1) = 390625 Hz - */ - rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); - IICCON = rIICCON; - - IICADD = slaveaddr; -} - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(uchar chip) -{ - /* - not implemented - */ - - printf("i2c_probe chip %d\n", (int) chip); - return -1; -} - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -#define S3C44B0X_rIIC_INTPEND (1<<4) -#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) -#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) -#define S3C44B0_IIC_TIMEOUT 100 - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - - int k, j, temp; - u32 rIICSTAT; - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - /* wait and check ACK */ - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - IICDS = addr; - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - /* - now we can start with the read operation... - */ - - IICDS = chip | 0x01; /* this is a read operation... */ - - rIICSTAT = 0x90; /*master recv*/ - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - for (j=0; j<len-1; j++) { - - /*clear pending bit to resume */ - - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); - IICCON = temp; - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - - buffer[j] = IICDS; /*save readed data*/ - - } /*end for(j)*/ - - /* - reading the last data - unset ACK generation - */ - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7)); - IICCON = temp; - - /* wait but NOT check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - buffer[j] = IICDS; /*save readed data*/ - - rIICSTAT = 0x90; /*master recv*/ - - /* Write operation Terminate sending STOP */ - IICSTAT = rIICSTAT; - /*Clear Int Pending Bit to RESUME*/ - temp = IICCON; - IICCON = temp & (~S3C44B0X_rIIC_INTPEND); - - IICCON = IICCON | (1<<7); /*restore ACK generation*/ - - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - int j, k; - u32 rIICSTAT, temp; - - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - IICDS = addr; - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - /* - now we can start with the read write operation - */ - for (j=0; j<len; j++) { - - IICDS = buffer[j]; /*prerare data to write*/ - - /*clear pending bit to resume*/ - - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); - IICCON = temp; - - /* wait but NOT check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - - udelay(2000); - } - - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - } /* end for(j) */ - - /* sending stop to terminate */ - rIICSTAT = 0xD0; /*master send*/ - IICSTAT = rIICSTAT; - /*Clear Int Pending Bit to RESUME*/ - temp = IICCON; - IICCON = temp & (~S3C44B0X_rIIC_INTPEND); - - return 0; -} diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f87e647881..a7170b49db 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -518,6 +518,8 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) return -1; mmc = malloc(sizeof(struct mmc)); + if (!mmc) + return -ENOMEM; sprintf(mmc->name, "FSL_SDHC"); regs = (struct fsl_esdhc *)cfg->esdhc_base; diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 378f8c513a..036c113ad3 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -155,6 +155,9 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, if (page_oob_size == 218) return 16; + + if (page_oob_size == 224) + return 16; } return 0; diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 9bab71a212..39240d9662 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -568,9 +568,14 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave, static void cpsw_slave_update_link(struct cpsw_slave *slave, struct cpsw_priv *priv, int *link) { - struct phy_device *phy = priv->phydev; + struct phy_device *phy; u32 mac_control = 0; + phy = priv->phydev; + + if (!phy) + return; + phy_startup(phy); *link = phy->link; @@ -947,6 +952,9 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) dev, slave->data->phy_if); + if (!phydev) + return -1; + phydev->supported &= supported; phydev->advertising = phydev->supported; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 690e5724b4..107cd6ecc5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -453,7 +453,7 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) udelay(100); /* * setup the MII gasket for RMII mode @@ -794,7 +794,7 @@ static int fec_recv(struct eth_device *dev) uint16_t bd_status; uint32_t addr, size, end; int i; - uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN); + ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); /* * Check if any critical events have happened diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 4b4f8b7983..0717cc6c31 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -135,7 +135,7 @@ struct ethernet_regs { uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ @@ -202,7 +202,7 @@ struct ethernet_regs { #define FEC_X_DES_ACTIVE_TDAR 0x01000000 #define FEC_R_DES_ACTIVE_RDAR 0x01000000 -#if defined(CONFIG_MX25) || defined(CONFIG_MX53) +#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) /* defines for MIIGSK */ /* RMII frequency control: 0=50MHz, 1=5MHz */ #define MIIGSK_CFGR_FRCONT (1 << 6) diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index f054470552..11b3d030e4 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,6 +13,8 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o +COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o +COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c new file mode 100644 index 0000000000..36e9024bf8 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65217.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <power/tps65217.h> + +/** + * tps65217_reg_read() - Generic function that can read a TPS65217 register + * @src_reg: Source register address + * @src_val: Address of destination variable + * @return: 0 for success, not 0 on failure. + */ +int tps65217_reg_read(uchar src_reg, uchar *src_val) +{ + return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1); +} + +/** + * tps65217_reg_write() - Generic function that can write a TPS65217 PMIC + * register or bit field regardless of protection + * level. + * + * @prot_level: Register password protection. Use + * TPS65217_PROT_LEVEL_NONE, + * TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2 + * @dest_reg: Register address to write. + * @dest_val: Value to write. + * @mask: Bit mask (8 bits) to be applied. Function will only + * change bits that are set in the bit mask. + * + * @return: 0 for success, not 0 on failure, as per the i2c API + */ +int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask) +{ + uchar read_val; + uchar xor_reg; + int ret; + + /* + * If we are affecting only a bit field, read dest_reg and apply the + * mask + */ + if (mask != TPS65217_MASK_ALL_BITS) { + ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK; + ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + } + + ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + + if (prot_level == TPS65217_PROT_LEVEL_2) { + ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + + ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * tps65217_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @dc_cntrl_reg: DC voltage control register to change. + * @volt_sel: New value for the voltage register + * @return: 0 for success, not 0 on failure. + */ +int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) +{ + if ((dc_cntrl_reg != TPS65217_DEFDCDC1) && + (dc_cntrl_reg != TPS65217_DEFDCDC2) && + (dc_cntrl_reg != TPS65217_DEFDCDC3)) + return 1; + + /* set voltage level */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel, + TPS65217_MASK_ALL_BITS)) + return 1; + + /* set GO bit to initiate voltage transition */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW, + TPS65217_DCDC_GO, TPS65217_DCDC_GO)) + return 1; + + return 0; +} diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c new file mode 100644 index 0000000000..7ee1160e0d --- /dev/null +++ b/drivers/power/pmic/pmic_tps65910.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <power/tps65910.h> + +/* + * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C + * interface. + * @return: 0 on success, not 0 on failure + */ +int tps65910_set_i2c_control(void) +{ + int ret; + uchar buf; + + /* VDD1/2 voltage selection register access by control i/f */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, + &buf, 1); + + if (ret) + return ret; + + buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, + &buf, 1); +} + +/* + * tps65910_voltage_update() - Voltage switching for MPU frequency switching. + * @module: mpu - 0, core - 1 + * @vddx_op_vol_sel: vdd voltage to set + * @return: 0 on success, not 0 on failure + */ +int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf; + unsigned int reg_offset; + int ret; + + if (module == MPU) + reg_offset = TPS65910_VDD1_OP_REG; + else + reg_offset = TPS65910_VDD2_OP_REG; + + /* Select VDDx OP */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + buf &= ~TPS65910_OP_REG_CMD_MASK; + + ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + /* Configure VDDx OP Voltage */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + buf &= ~TPS65910_OP_REG_SEL_MASK; + buf |= vddx_op_vol_sel; + + ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel) + return 1; + + return 0; +} diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index b477c23ebd..dcc0632ff2 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -53,7 +53,6 @@ COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o COBJS-$(CONFIG_RTC_RV3029) += rv3029.o COBJS-$(CONFIG_RTC_RX8025) += rx8025.o COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o -COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o COBJS-$(CONFIG_RTC_X1205) += x1205.o COBJS := $(sort $(COBJS-y)) diff --git a/drivers/rtc/s3c44b0_rtc.c b/drivers/rtc/s3c44b0_rtc.c deleted file mode 100644 index de7898cc34..0000000000 --- a/drivers/rtc/s3c44b0_rtc.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * S3C44B0 CPU specific code - */ - -#include <common.h> -#include <command.h> -#include <asm/hardware.h> -#include <rtc.h> - -int rtc_get (struct rtc_time* tm) -{ - RTCCON |= 1; - tm->tm_year = bcd2bin(BCDYEAR); - tm->tm_mon = bcd2bin(BCDMON); - tm->tm_wday = bcd2bin(BCDDATE); - tm->tm_mday = bcd2bin(BCDDAY); - tm->tm_hour = bcd2bin(BCDHOUR); - tm->tm_min = bcd2bin(BCDMIN); - tm->tm_sec = bcd2bin(BCDSEC); - - if (tm->tm_sec==0) { - /* we have to re-read the rtc data because of the "one second deviation" problem */ - /* see RTC datasheet for more info about it */ - tm->tm_year = bcd2bin(BCDYEAR); - tm->tm_mon = bcd2bin(BCDMON); - tm->tm_mday = bcd2bin(BCDDAY); - tm->tm_wday = bcd2bin(BCDDATE); - tm->tm_hour = bcd2bin(BCDHOUR); - tm->tm_min = bcd2bin(BCDMIN); - tm->tm_sec = bcd2bin(BCDSEC); - } - - RTCCON &= ~1; - - if(tm->tm_year >= 70) - tm->tm_year += 1900; - else - tm->tm_year += 2000; - - return 0; -} - -int rtc_set (struct rtc_time* tm) -{ - if(tm->tm_year < 2000) - tm->tm_year -= 1900; - else - tm->tm_year -= 2000; - - RTCCON |= 1; - BCDYEAR = bin2bcd(tm->tm_year); - BCDMON = bin2bcd(tm->tm_mon); - BCDDAY = bin2bcd(tm->tm_mday); - BCDDATE = bin2bcd(tm->tm_wday); - BCDHOUR = bin2bcd(tm->tm_hour); - BCDMIN = bin2bcd(tm->tm_min); - BCDSEC = bin2bcd(tm->tm_sec); - RTCCON &= 1; - - return 0; -} - -void rtc_reset (void) -{ - RTCCON |= 1; - BCDYEAR = 0; - BCDMON = 0; - BCDDAY = 0; - BCDDATE = 0; - BCDHOUR = 0; - BCDMIN = 0; - BCDSEC = 0; - RTCCON &= 1; -} diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 4c45bfa363..e1fd7a5dc8 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -31,7 +31,6 @@ COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o -COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 35dc61e020..df2b84aaaf 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -156,7 +156,6 @@ serial_initfunc(lh7a40x_serial_initialize); serial_initfunc(max3100_serial_initialize); serial_initfunc(mxc_serial_initialize); serial_initfunc(pl01x_serial_initialize); -serial_initfunc(s3c44b0_serial_initialize); serial_initfunc(sa1100_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(arm_dcc_initialize); @@ -250,7 +249,6 @@ void serial_initialize(void) max3100_serial_initialize(); mxc_serial_initialize(); pl01x_serial_initialize(); - s3c44b0_serial_initialize(); sa1100_serial_initialize(); sh_serial_initialize(); arm_dcc_initialize(); diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c deleted file mode 100644 index 2a07498c1e..0000000000 --- a/drivers/serial/serial_s3c44b0.c +++ /dev/null @@ -1,216 +0,0 @@ -pyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * ght 2002-2004 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* flush serial input queue. returns 0 on success or negative error - * number otherwise - */ -static int serial_flush_input(void) -{ - volatile u32 tmp; - - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0&0x01) { - tmp = REGB(URXH0); - } - - return 0; -} - - -/* flush output queue. returns 0 on success or negative error number - * otherwise - */ -static int serial_flush_output(void) -{ - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & 0x02)) { - } - - return 0; -} - - -static void s3c44b0_serial_setbrg(void) -{ - u32 divisor = 0; - - /* get correct divisor */ - switch(gd->baudrate) { - - case 1200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 3124; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 3905; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 9600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 390; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 487; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 19200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 194; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 243; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 38400: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 97; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 121; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 57600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 64; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 80; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 115200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 32; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 40; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - } - - serial_flush_output(); - serial_flush_input(); - UFCON0 = 0x0; - ULCON0 = 0x03; - UCON0 = 0x05; - UBRDIV0 = divisor; - - UFCON1 = 0x0; - ULCON1 = 0x03; - UCON1 = 0x05; - UBRDIV1 = divisor; - - for(divisor=0; divisor<100; divisor++) { - /* NOP */ - } -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int s3c44b0_serial_init(void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void s3c44b0_serial_putc(const char c) -{ - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & 0x02)); - - UTXH0 = (unsigned char)c; - - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n') - serial_putc('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int s3c44b0_serial_tstc(void) -{ - return (UTRSTAT0 & 0x01); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int s3c44b0_serial_getc(void) -{ - int rv; - - for(;;) { - rv = s3c44b0_serial_tstc(); - - if(rv > 0) - return URXH0; - } -} - -static struct serial_device s3c44b0_serial_drv = { - .name = "s3c44b0_serial", - .start = s3c44b0_serial_init, - .stop = NULL, - .setbrg = s3c44b0_serial_setbrg, - .putc = s3c44b0_serial_putc, - .puts = default_serial_puts, - .getc = s3c44b0_serial_getc, - .tstc = s3c44b0_serial_tstc, -}; - -void s3c44b0_serial_initialize(void) -{ - serial_register(&s3c44b0_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &s3c44b0_serial_drv; -} diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 978fdf9cb5..348247050a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -171,6 +171,7 @@ "run mmcboot;" \ "setenv mmcdev 1; " \ "setenv bootpart 1:2; " \ + "setenv mmcroot /dev/mmcblk1p2 ro; " \ "run mmcboot;" \ "run nandboot;" @@ -190,8 +191,13 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_MULTI_EEPROMS +/* PMIC support */ +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 + /* SPL */ #ifndef CONFIG_NOR_BOOT +#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_YMODEM_SUPPORT /* CPSW support */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h new file mode 100644 index 0000000000..e7e258fa60 --- /dev/null +++ b/include/configs/apf27.h @@ -0,0 +1,388 @@ +/* + * + * Configuration settings for the Armadeus Project motherboard APF27 + * + * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_ENV_VERSION 10 +#define CONFIG_IDENT_STRING " apf27 patch 3.10" +#define CONFIG_BOARD_NAME apf27 + +/* + * SoC configurations + */ +#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */ +#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */ +#define CONFIG_MACH_TYPE 1698 /* APF27 */ +#define CONFIG_SYS_GENERIC_BOARD + +/* + * Enable the call to miscellaneous platform dependent initialization. + */ +#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */ + +/* + * Board display option + */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO + +/* + * SPL + */ +#define CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_TEXT_BASE 0xA0000000 + +/* NAND boot config */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 + +#define CONFIG_HOSTNAME CONFIG_BOARD_NAME +#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" + +/* + * U-Boot Commands + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_BSP /* Board Specific functions */ +#define CONFIG_CMD_CACHE /* icache, dcache */ +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_DNS +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII /* MII support */ +#define CONFIG_CMD_MMC +#define CONFIG_CMD_MTDPARTS /* MTD partition support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING /* ping support */ +#define CONFIG_CMD_SETEXPR /* setexpr support */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_POPULATED 1 +#define CONFIG_NR_DRAM_BANKS 2 + +#define ACFG_SDRAM_MBYTE_SYZE 64 + +#define PHYS_SDRAM_1 0xA0000000 +#define PHYS_SDRAM_2 0xB0000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) +#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ +#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ + + PHYS_SDRAM_1_SIZE - 0x0100000) + +#define CONFIG_SYS_TEXT_BASE 0xA0000800 + +/* + * FLASH organization + */ +#define ACFG_MONITOR_OFFSET 0x00000000 +#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ +#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ +#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ +#define CONFIG_FIRMWARE_OFFSET 0x00200000 +#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ +#define CONFIG_KERNEL_OFFSET 0x00300000 +#define CONFIG_ROOTFS_OFFSET 0x00800000 + +#define CONFIG_MTDMAP "mxc_nand.0" +#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP +#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \ + ":1M(u-boot)ro," \ + "512K(env)," \ + "512K(env2)," \ + "512K(firmware)," \ + "512K(dtb)," \ + "5M(kernel)," \ + "-(rootfs)" + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */ +#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 16 /* max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_PREBOOT "run check_flash check_env;" + + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG /* send initrd params */ + +#define CONFIG_OF_LIBFDT + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" +#define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \ + __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \ + " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " + +#define ACFG_CONSOLE_DEV ttySMX0 +#define CONFIG_BOOTCOMMAND "run ubifsboot" +#define CONFIG_SYS_AUTOLOAD "no" +/* + * Default load address for user programs and kernel + */ +#define CONFIG_LOADADDR 0xA0000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ + "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,6\0" \ + "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ + "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ + "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ + "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ + "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ + "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ + "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ + "kernel_addr_r=A0000000\0" \ + "check_env=if test -n ${flash_env_version}; " \ + "then env default env_version; " \ + "else env set flash_env_version ${env_version}; env save; "\ + "fi; " \ + "if itest ${flash_env_version} < ${env_version}; then " \ + "echo \"*** Warning - Environment version" \ + " change suggests: run flash_reset_env; reset\"; "\ + "env default flash_reset_env; "\ + "fi; \0" \ + "check_flash=nand lock; nand unlock ${env_addr}; \0" \ + "flash_reset_env=env default -f -a; saveenv; run update_env;" \ + "echo Flash environment variables erased!\0" \ + "download_uboot=tftpboot ${loadaddr} ${board_name}" \ + "-u-boot-with-spl.bin\0" \ + "flash_uboot=nand unlock ${u-boot_addr} ;" \ + "nand erase.part u-boot;" \ + "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ + "then nand lock; nand unlock ${env_addr};" \ + "echo Flashing of uboot succeed;" \ + "else echo Flashing of uboot failed;" \ + "fi; \0" \ + "update_uboot=run download_uboot flash_uboot\0" \ + "download_env=tftpboot ${loadaddr} ${board_name}" \ + "-u-boot-env.txt\0" \ + "flash_env=env import -t ${loadaddr}; env save; \0" \ + "update_env=run download_env flash_env\0" \ + "update_all=run update_env update_uboot\0" \ + "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ + +/* + * Serial Driver + */ +#define CONFIG_MXC_UART +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* + * GPIO + */ +#define CONFIG_MXC_GPIO + +/* + * NOR + */ + +/* + * NAND + */ +#define CONFIG_NAND_MXC + +#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 +#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 +#define NAND_MAX_CHIPS 1 + +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_NAND_QUIET 1 + +/* + * Partitions & Filsystems + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + +/* + * UBIFS + */ +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* + * Ethernet (on SOC imx FEC) + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII /* MII PHY management */ + +/* + * FPGA + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_FPGA +#endif +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_CHECK_CTRLC +#define CONFIG_SYS_FPGA_CHECK_ERROR + +/* + * Fuses - IIM + */ +#ifdef CONFIG_CMD_IMX_FUSE +#define IIM_MAC_BANK 0 +#define IIM_MAC_ROW 5 +#define IIM0_SCC_KEY 11 +#define IIM1_SUID 1 +#endif + +/* + * I2C + */ + +#ifdef CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_BASE IMX_I2C1_BASE +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES { } + +#ifdef CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ +#endif /* CONFIG_CMD_EEPROM */ +#endif /* CONFIG_CMD_I2C */ + +/* + * SD/MMC + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 +#endif + +/* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1374 +#define CONFIG_SYS_RTC_BUS_NUM 0 +#endif /* CONFIG_CMD_DATE */ + +/* + * Clocks + */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ + +/* + * PLL + * + * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 + * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| + */ +#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ + +#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ +/* micron 64MB */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ +#endif + +#if (ACFG_SDRAM_MBYTE_SYZE == 128) +/* micron 128MB */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#endif + +#if (ACFG_SDRAM_MBYTE_SYZE == 256) +/* micron 256MB */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ +#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 4fbe768cbc..7b120de213 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -14,7 +14,13 @@ #define CONFIG_DRA7XX -#define CONFIG_ENV_IS_NOWHERE /* For now. */ +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_CMD_SAVEENV #define CONSOLEDEV "ttyO0" #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index ccc7bd0a8a..b8e672f82b 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -83,7 +83,7 @@ * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* * sdram diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 68b225af9c..a25b20e4af 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -23,7 +23,6 @@ /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA0000000 -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index a3dd74a4a2..3229bc70d8 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -16,7 +16,11 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0" #define CONFIG_MMCROOT "/dev/mmcblk1p2" +#if defined(CONFIG_MX6Q) #define CONFIG_DEFAULT_FDT_FILE "imx6q-sabresd.dtb" +#elif defined(CONFIG_MX6DL) +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabresd.dtb" +#endif #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #include "mx6sabre_common.h" diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ca8f2f607d..792f17cea4 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -44,6 +44,20 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index e2b4de7414..2fff0beffa 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -201,6 +201,7 @@ /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT /* * Place the image at the start of the ROM defined image space. * We limit our size to the ROM-defined downloaded image area, and use the diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h new file mode 100644 index 0000000000..a85eb1c3fc --- /dev/null +++ b/include/configs/sansa_fuze_plus.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__ +#define __CONFIGS_SANSA_FUZE_PLUS_H__ + +/* System configurations */ +#define CONFIG_MX23 /* i.MX23 SoC */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_VIDEO +#define CONFIG_CMD_MEMTEST + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_OVERWRITE + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_FONT_4X6 +#define CONFIG_VIDEO_MXS_MODE_SYSTEM +#define CONFIG_SYS_BLACK_IN_WRITE +#define LCD_BPP LCD_COLOR16 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#endif + +/* The rest of the configuration is shared */ +#include <configs/mxs.h> + +#endif /* __CONFIGS_SANSA_FUZE_PLUS_H__ */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 665cfc3cfa..442a9841ca 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -99,12 +99,10 @@ #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_IMX_HDMI -#if defined(CONFIG_MX6DL) +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb" #elif defined(CONFIG_MX6Q) #define CONFIG_DEFAULT_FDT_FILE "imx6q-wandboard.dtb" -#elif defined(CONFIG_MX6S) -#define CONFIG_DEFAULT_FDT_FILE "imx6s-wandboard.dtb" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h new file mode 100644 index 0000000000..022bc95927 --- /dev/null +++ b/include/configs/xfi3.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_XFI3_H__ +#define __CONFIGS_XFI3_H__ + +/* System configurations */ +#define CONFIG_MX23 /* i.MX23 SoC */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_VIDEO + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_OVERWRITE + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_FONT_4X6 +#define CONFIG_VIDEO_MXS_MODE_SYSTEM +#define CONFIG_SYS_BLACK_IN_WRITE +#define LCD_BPP LCD_COLOR16 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#endif + +/* The rest of the configuration is shared */ +#include <configs/mxs.h> + +#endif /* __CONFIGS_XFI3_H__ */ diff --git a/include/power/tps65217.h b/include/power/tps65217.h new file mode 100644 index 0000000000..297c4cbd99 --- /dev/null +++ b/include/power/tps65217.h @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the TRM at http://www.ti.com/product/tps65217a + */ + +#ifndef __POWER_TPS65217_H__ +#define __POWER_TPS65217_H__ + +/* I2C chip address */ +#define TPS65217_CHIP_PM 0x24 + +/* Registers */ +enum { + TPS65217_CHIPID = 0x00, + TPS65217_POWER_PATH, + TPS65217_INTERRUPT, + TPS65217_CHGCONFIG0, + TPS65217_CHGCONFIG1, + TPS65217_CHGCONFIG2, + TPS65217_CHGCONFIG3, + TPS65217_WLEDCTRL1, + TPS65217_WLEDCTRL2, + TPS65217_MUXCTRL, + TPS65217_STATUS, + TPS65217_PASSWORD, + TPS65217_PGOOD, + TPS65217_DEFPG, + TPS65217_DEFDCDC1, + TPS65217_DEFDCDC2, + TPS65217_DEFDCDC3, + TPS65217_DEFSLEW, + TPS65217_DEFLDO1, + TPS65217_DEFLDO2, + TPS65217_DEFLS1, + TPS65217_DEFLS2, + TPS65217_ENABLE, + TPS65217_DEFUVLO, + TPS65217_SEQ1, + TPS65217_SEQ2, + TPS65217_SEQ3, + TPS65217_SEQ4, + TPS65217_SEQ5, + TPS65217_SEQ6, + TPS65217_PMIC_NUM_OF_REGS, +}; + +#define TPS65217_PROT_LEVEL_NONE 0x00 +#define TPS65217_PROT_LEVEL_1 0x01 +#define TPS65217_PROT_LEVEL_2 0x02 + +#define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00 +#define TPS65217_PASSWORD_UNLOCK 0x7D + +#define TPS65217_DCDC_GO 0x80 + +#define TPS65217_MASK_ALL_BITS 0xFF + +#define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03 +#define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00 +#define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01 +#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 +#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 + +#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09 +#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F +#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11 + +#define TPS65217_LDO_MASK 0x1F +#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06 +#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F + +#define TPS65217_PWR_SRC_USB_BITMASK 0x4 +#define TPS65217_PWR_SRC_AC_BITMASK 0x8 + +int tps65217_reg_read(uchar src_reg, uchar *src_val); +int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask); +int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +#endif /* __POWER_TPS65217_H__ */ diff --git a/include/power/tps65910.h b/include/power/tps65910.h new file mode 100644 index 0000000000..ca8430145b --- /dev/null +++ b/include/power/tps65910.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the TRM at http://www.ti.com/product/tps65910 + */ +#ifndef __POWER_TPS65910_H__ +#define __POWER_TPS65910_H__ + +#define MPU 0 +#define CORE 1 + +#define TPS65910_SR_I2C_ADDR 0x12 +#define TPS65910_CTRL_I2C_ADDR 0x2D + +/* PMIC Register offsets */ +enum { + TPS65910_VDD1_REG = 0x21, + TPS65910_VDD1_OP_REG = 0x22, + TPS65910_VDD2_REG = 0x24, + TPS65910_VDD2_OP_REG = 0x25, + TPS65910_DEVCTRL_REG = 0x3F, +}; + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define TPS65910_VGAIN_SEL_MASK (0x3 << 6) +#define TPS65910_ILMAX_MASK (0x1 << 5) +#define TPS65910_TSTEP_MASK (0x7 << 2) +#define TPS65910_ST_MASK (0x3) + +#define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6) +#define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6) +#define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define TPS65910_REG_ILMAX_1_0_A (0x0 << 5) +#define TPS65910_REG_ILMAX_1_5_A (0x1 << 5) + +#define TPS65910_REG_TSTEP_ (0x0 << 2) +#define TPS65910_REG_TSTEP_12_5 (0x1 << 2) +#define TPS65910_REG_TSTEP_9_4 (0x2 << 2) +#define TPS65910_REG_TSTEP_7_5 (0x3 << 2) +#define TPS65910_REG_TSTEP_6_25 (0x4 << 2) +#define TPS65910_REG_TSTEP_4_7 (0x5 << 2) +#define TPS65910_REG_TSTEP_3_12 (0x6 << 2) +#define TPS65910_REG_TSTEP_2_5 (0x7 << 2) + +#define TPS65910_REG_ST_OFF (0x0) +#define TPS65910_REG_ST_ON_HI_POW (0x1) +#define TPS65910_REG_ST_OFF_1 (0x2) +#define TPS65910_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define TPS65910_OP_REG_SEL (0x7F) + +#define TPS65910_OP_REG_CMD_MASK (0x1 << 7) +#define TPS65910_OP_REG_CMD_OP (0x0 << 7) +#define TPS65910_OP_REG_CMD_SR (0x1 << 7) + +#define TPS65910_OP_REG_SEL_MASK (0x7F) +#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */ +#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */ +#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ +#define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +int tps65910_set_i2c_control(void); +int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel); +#endif /* __POWER_TPS65910_H__ */ diff --git a/spl/Makefile b/spl/Makefile index 174d0a7fc4..b366ac2bb7 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -87,7 +87,8 @@ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o -LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o +LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \ + drivers/power/pmic/libpmic.o LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o diff --git a/tools/imximage.c b/tools/imximage.c index c87669b985..32e4efe423 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -259,7 +259,7 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len, csf_ptr = &fhdr_v2->csf; } -static void set_hdr_func(struct imx_header *imxhdr) +static void set_hdr_func(void) { switch (imximage_version) { case IMXIMAGE_V1: @@ -358,7 +358,7 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token, exit(EXIT_FAILURE); } cmd_ver_first = 1; - set_hdr_func(imxhdr); + set_hdr_func(); break; case CMD_BOOT_FROM: imximage_ivt_offset = get_table_entry_id(imximage_boot_offset, @@ -563,7 +563,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, /* Be able to detect if the cfg file has no BOOT_FROM tag */ imximage_ivt_offset = FLASH_OFFSET_UNDEFINED; imximage_csf_size = 0; - set_hdr_func(imxhdr); + set_hdr_func(); /* Parse dcd configuration file */ dcd_len = parse_cfg_file(imxhdr, params->imagename); @@ -631,7 +631,7 @@ static int imximage_generate(struct mkimage_params *params, /* Be able to detect if the cfg file has no BOOT_FROM tag */ imximage_ivt_offset = FLASH_OFFSET_UNDEFINED; imximage_csf_size = 0; - set_hdr_func(imxhdr); + set_hdr_func(); /* Parse dcd configuration file */ parse_cfg_file(&imximage_header, params->imagename); diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 1060cbf605..90b21737b9 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -379,7 +379,7 @@ static uint8_t *mx28_nand_fcb_block(struct mx28_nand_fcb *fcb) return block; } -static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, char *buf) +static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, uint8_t *buf) { uint32_t offset; uint8_t *fcbblock; @@ -393,13 +393,15 @@ static int mx28_nand_write_fcb(struct mx28_nand_fcb *fcb, char *buf) for (i = 0; i < STRIDE_PAGES * STRIDE_COUNT; i += STRIDE_PAGES) { offset = i * nand_writesize; memcpy(buf + offset, fcbblock, nand_writesize + nand_oobsize); + /* Mark the NAND page is OK. */ + buf[offset + nand_writesize] = 0xff; } free(fcbblock); return ret; } -static int mx28_nand_write_dbbt(struct mx28_nand_dbbt *dbbt, char *buf) +static int mx28_nand_write_dbbt(struct mx28_nand_dbbt *dbbt, uint8_t *buf) { uint32_t offset; int i = STRIDE_PAGES * STRIDE_COUNT; @@ -413,7 +415,7 @@ static int mx28_nand_write_dbbt(struct mx28_nand_dbbt *dbbt, char *buf) } static int mx28_nand_write_firmware(struct mx28_nand_fcb *fcb, int infd, - char *buf) + uint8_t *buf) { int ret; off_t size; @@ -462,7 +464,7 @@ static int mx28_create_nand_image(int infd, int outfd) struct mx28_nand_fcb *fcb; struct mx28_nand_dbbt *dbbt; int ret = -1; - char *buf; + uint8_t *buf; int size; ssize_t wr_size; |