diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-10-12 15:57:11 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2018-10-12 16:34:40 +0800 |
| commit | d45d0d06783602f0d7387406c1d5185bd9b5a4cc (patch) | |
| tree | 8ed9b0c0caad77dc55b859fb9ca8a05f163d89e9 | |
| parent | 7e7d6b34d209ad0e82c91bca4c082cb82e8a6d71 (diff) | |
MLK-19907 imx8m: ddr4: Update the refresh_mode setting
Update the refresh_mode setting. Clear the RFSHCTL3.refresh_mode bit
to set it to normal_mode.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit dac64635e978fb73ecbe83016a307be6ac7d5f0d)
| -rw-r--r-- | drivers/ddr/imx8m/ddr4_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ddr/imx8m/ddr4_init.c b/drivers/ddr/imx8m/ddr4_init.c index 47b21441d2..cdb838764a 100644 --- a/drivers/ddr/imx8m/ddr4_init.c +++ b/drivers/ddr/imx8m/ddr4_init.c @@ -48,7 +48,7 @@ void ddr_init(struct dram_timing_info *dram_timing) /* config the uMCTL2's registers */ ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); - reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + reg32_write(DDRC_RFSHCTL3(0), 0x00000001); /* RESET: <ctn> DEASSERTED */ /* RESET: <a Port 0 DEASSERTED(0) */ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); @@ -91,7 +91,7 @@ void ddr_init(struct dram_timing_info *dram_timing) reg32_write(DDRC_PWRCTL(0), 0x0000088); reg32_write(DDRC_PCTRL_0(0), 0x00000001); - reg32_write(DDRC_RFSHCTL3(0), 0x00000010); /* dis_auto-refresh is set to 0 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); /* dis_auto-refresh is set to 0 */ /* save the dram timing config into memory */ dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); |