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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2020-11-12 18:34:50 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2020-11-19 20:31:31 +0100
commited39664c84cf4936ba37f2dc6da34bc0c4f4c4a5 (patch)
tree2f0c514195ed76c4ce5fa3f74b7e2a7ed6a0bb68
parent416025ff878ba7d4c2723a3ff5420b32b424b681 (diff)
board: toradex: add verdin imx8m plus support
This adds initial minimal support for the Toradex Verdin iMX8M Plus Quad 4GB WB IT V1.0A and Toradex Verdin iMX8M Plus Quad 2GB V1.0A modules. They are strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports booting from the on-module eMMC or, if the recovery button/pin is asserted, via USB serial download aka SDP support. Functionality wise the following is known to be working: - eMMC, 8-bit and 4-bit MMC/SD card slots - Ethernet (but only 2nd one available on the Verdin Development board) - GPIOs - I2C Boot sequence is: SPL ---> ATF (TF-A) ---> U-boot proper ATF, U-boot proper and u-boot.dtb images are packed into a FIT image, loaded by SPL. Boot: U-Boot SPL 2020.04-00217-gfad48768ba (Nov 18 2020 - 14:22:31 +0100) DDRINFO: start DRAM init DDRINFO: DRAM rate 4000MTS DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Trying to boot from BOOTROM Find FIT header 0x4803afa0, size 855 Need continue download 1024 Download 833424, total fit 834544 NOTICE: BL31: v2.2(release):imx_5.4.24_er3-6-g0a236bda5 NOTICE: BL31: Built : 13:40:19, Nov 12 2020 U-Boot 2020.04-00217-gfad48768ba (Nov 18 2020 - 14:22:31 +0100) alloc_simple() alloc space exhausted CPU: i.MX8MP[8] rev1.0 1800 MHz (running at 1200 MHz) CPU: Commercial temperature grade (0C to 95C) at 46C Reset cause: POR DRAM: 4 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 In: serial Out: serial Err: serial Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0A, Serial# 06775455 MISSING TORADEX CARRIER CONFIG BLOCKS BuildInfo: - ATF 0a236bd - U-Boot 2020.04-00217-gfad48768ba Detect USB boot. Will enter fastboot mode! Net: Warning: ethernet@30bf0000 (eth1) using random MAC address - 56:c0:c6:84:63:a0 eth0: ethernet@30be0000, eth1: ethernet@30bf0000 [PRIME] Fastboot: Normal Boot from USB for mfgtools *** Warning - Use default environment for mfgtools , using default environment Run bootcmd_mfg: fastboot 0 Hit any key to stop autoboot: 0 Verdin iMX8MP # Related-to: ELB-3208 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat
-rw-r--r--.gitlab-ci.yml2
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/imx8mp-verdin-u-boot.dtsi134
-rw-r--r--arch/arm/dts/imx8mp-verdin.dts625
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig7
-rw-r--r--board/toradex/verdin-imx8mp/Kconfig39
-rw-r--r--board/toradex/verdin-imx8mp/MAINTAINERS10
-rw-r--r--board/toradex/verdin-imx8mp/Makefile11
-rw-r--r--board/toradex/verdin-imx8mp/imximage.cfg17
-rw-r--r--board/toradex/verdin-imx8mp/lpddr4_timing.c1854
-rw-r--r--board/toradex/verdin-imx8mp/spl.c262
-rw-r--r--board/toradex/verdin-imx8mp/verdin-imx8mp.c418
-rw-r--r--configs/verdin-imx8mp_defconfig124
-rw-r--r--include/configs/verdin-imx8mp.h159
14 files changed, 3662 insertions, 1 deletions
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 39272d05a8..cfe5657bf8 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -71,7 +71,7 @@ build all 64bit Toradex boards:
variables:
ARCH: arm64
CROSS_COMPILE: /opt/gcc-7.3.0-nolibc/aarch64-linux/bin/aarch64-linux-
- TARGETS: "colibri-imx8x apalis-imx8x apalis-imx8 verdin-imx8mm"
+ TARGETS: "apalis-imx8 apalis-imx8x colibri-imx8x verdin-imx8mm verdin-imx8mp"
script: |
for TARGET in $TARGETS; do
echo -ne "#\n#\n#\n#\n#\n#\n# Building ${TARGET}\n#\n#\n#\n#\n#\n#\n"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4f1d2104c8..638fbdfd3b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -794,6 +794,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-ddr4-val.dtb \
imx8mq-evk.dtb \
imx8mp-evk.dtb \
+ imx8mp-verdin.dtb \
imx8mm-ab2.dtb \
imx8mn-ddr4-ab2.dtb \
imx8mn-ab2.dtb
diff --git a/arch/arm/dts/imx8mp-verdin-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi
new file mode 100644
index 0000000000..47fe170cbf
--- /dev/null
+++ b/arch/arm/dts/imx8mp-verdin-u-boot.dtsi
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+
+};
+
+&osc_32k {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&i2c3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&eqos {
+ compatible = "fsl,imx-eqos";
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
diff --git a/arch/arm/dts/imx8mp-verdin.dts b/arch/arm/dts/imx8mp-verdin.dts
new file mode 100644
index 0000000000..6dcb5b7455
--- /dev/null
+++ b/arch/arm/dts/imx8mp-verdin.dts
@@ -0,0 +1,625 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mp.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Plus";
+ compatible = "toradex,verdin-imx8mp", "fsl,imx8mp";
+
+ aliases {
+ eeprom0 = &eeprom_module;
+ eeprom1 = &eeprom_carrier;
+ eeprom2 = &eeprom_mipi_dsi;
+ };
+
+ chosen {
+ bootargs = "console=ttymxc2,115200 earlycon";
+ stdout-path = &uart3;
+ };
+
+ reg_ethphy: regulator-ethphy {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
+ off-on-delay = <500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_eth>;
+ regulator-boot-on;
+ regulator-name = "V3.3_ETH";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <200000>;
+ };
+
+ reg_usb1_host_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_host_vbus";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* USB_2_EN */
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "V3.3_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; /* SD_1_PWR_EN */
+ enable-active-high;
+ startup-delay-us = <2000>;
+ };
+};
+
+&eqos {
+ phy-handle = <&ethphy0>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&reg_ethphy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,led-mode = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+&fec {
+ fsl,magic-packet;
+ phy-handle = <&ethphy1>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ micrel,led-mode = <0>;
+ };
+ };
+};
+
+/* Verdin PMIC_I2C */
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pmic: pca9450@25 {
+ reg = <0x25>;
+ compatible = "nxp,pca9450c";
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9450,pmic-buck2-uses-i2c-dvs;
+ /* Run/Standby voltage */
+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+ buck1_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "buck1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "buck2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "buck4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "buck5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "buck6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: regulator@10 { /* +V3.3_1.8_SD */
+ reg = <10>;
+ regulator-compatible = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+
+ /* Epson RX8130 real time clock on carrier board */
+ rtc: rx8130@32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ };
+
+ eeprom_module: eeprom@50 {
+ compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+};
+
+/* Verdin I2C2 DSI */
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* Verdin I2C4 CSI */
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pca6416: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+/* Verdin I2C1 */
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ /* EEPROM on MIPI-DSI to HDMI adapter */
+ eeprom_mipi_dsi: eeprom@50 {
+ compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+
+ /* EEPROM on Verdin Development board */
+ eeprom_carrier: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
+ pagesize = <16>;
+ reg = <0x57>;
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* Verdin UART3 */
+&uart3 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* Verdin SDIO 1 */
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <&reg_usdhc2_vmmc>;
+ status = "okay";
+};
+
+/* On-module eMMC */
+&usdhc3 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>,
+ <&pinctrl_gpio4>, <&pinctrl_gpio5>, <&pinctrl_gpio6>,
+ <&pinctrl_gpio7>, <&pinctrl_gpio8>;
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
+ >;
+ };
+
+ /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184 /* SODIMM 206 */
+ >;
+ };
+
+ pinctrl_gpio2: gpio2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x184 /* SODIMM 208 */
+ >;
+ };
+
+ pinctrl_gpio3: gpio3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184 /* SODIMM 210 */
+ >;
+ };
+
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184 /* SODIMM 212 */
+ >;
+ };
+
+ pinctrl_gpio5: gpio5grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184 /* SODIMM 216 */
+ >;
+ };
+
+ pinctrl_gpio6: gpio6grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184 /* SODIMM 218 */
+ >;
+ };
+
+ pinctrl_gpio7: gpio7grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184 /* SODIMM 220 */
+ >;
+ };
+
+ pinctrl_gpio8: gpio8grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184 /* SODIMM 222 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
+ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
+ MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
+ >;
+ };
+
+ pinctrl_reg_eth: regethgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x41
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usb1_vbus: usb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index fb6dfe3355..87666cb51d 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -129,6 +129,12 @@ config TARGET_VERDIN_IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_VERDIN_IMX8MP
+ bool "Support Toradex Verdin iMX8M Plus module"
+ select IMX8MP
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
@@ -139,5 +145,6 @@ source "board/freescale/imx8mm_val/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
+source "board/toradex/verdin-imx8mp/Kconfig"
endif
diff --git a/board/toradex/verdin-imx8mp/Kconfig b/board/toradex/verdin-imx8mp/Kconfig
new file mode 100644
index 0000000000..4400e4522d
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/Kconfig
@@ -0,0 +1,39 @@
+if TARGET_VERDIN_IMX8MP
+
+config SYS_BOARD
+ default "verdin-imx8mp"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "verdin-imx8mp"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_CFG_BLOCK_EXTRA
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_HAVE_EEPROM_EXTRA
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "2"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+ default y
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/verdin-imx8mp/MAINTAINERS b/board/toradex/verdin-imx8mp/MAINTAINERS
new file mode 100644
index 0000000000..3c788420a4
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/MAINTAINERS
@@ -0,0 +1,10 @@
+Verdin iMX8M Plus
+M: Igor Opaniuk <igor.opaniuk@toradex.com>
+W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
+S: Maintained
+F: arch/arm/dts/imx8mp-verdin.dts
+F: arch/arm/dts/imx8mp-verdin-u-boot.dtsi
+F: board/toradex/verdin-imx8mp/
+F: configs/verdin-imx8mp_defconfig
+F: doc/board/toradex/verdin-imx8mp.rst
+F: include/configs/verdin-imx8mp.h
diff --git a/board/toradex/verdin-imx8mp/Makefile b/board/toradex/verdin-imx8mp/Makefile
new file mode 100644
index 0000000000..287601390b
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Toradex
+#
+
+obj-y += verdin-imx8mp.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/toradex/verdin-imx8mp/imximage.cfg b/board/toradex/verdin-imx8mp/imximage.cfg
new file mode 100644
index 0000000000..26bda25ac3
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/imximage.cfg
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Toradex
+ */
+
+#define __ASSEMBLY__
+
+FIT
+ROM_VERSION v2
+BOOT_FROM emmc_fastboot
+LOADER spl/u-boot-spl-ddr.bin 0x920000
+SECOND_LOADER u-boot.itb 0x40200000 0x60000
+
+DDR_FW lpddr4_pmu_train_1d_imem_201904.bin
+DDR_FW lpddr4_pmu_train_1d_dmem_201904.bin
+DDR_FW lpddr4_pmu_train_2d_imem_201904.bin
+DDR_FW lpddr4_pmu_train_2d_dmem_201904.bin
diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c
new file mode 100644
index 0000000000..cab984c3a0
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -0,0 +1,1854 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x1303 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
+ { 0x3d400070, 0x61027f10 },
+ { 0x3d400074, 0x7b0 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x807bf },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x501 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x9121c1c },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1001 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1001 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x1 },
+ { 0x100a1, 0x6 },
+ { 0x100a2, 0x4 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x2 },
+ { 0x100a5, 0x7 },
+ { 0x100a6, 0x5 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x6 },
+ { 0x120a7, 0x7 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x4 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x2 },
+ { 0x130a5, 0x6 },
+ { 0x130a6, 0x5 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x18 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x3e8 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P1 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P2 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x7d },
+ { 0x2000c, 0xfa },
+ { 0x2000d, 0x9c4 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
+
diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c
new file mode 100644
index 0000000000..374538e133
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/spl.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <cpu_func.h>
+#include <errno.h>
+#include <fsl_esdhc_imx.h>
+#include <hang.h>
+#include <mmc.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
+ return BOOT_DEVICE_BOOTROM;
+#else
+ switch (boot_dev_spl) {
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC2;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_NOR;
+ case NAND_BOOT:
+ return BOOT_DEVICE_NAND;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+#endif
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
+ PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+#define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ /* esdhc_base, sdhc_clk, max_bus_width */
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR, 0, 8},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC2 (SD card)
+ * mmc1 USDHC3 (eMMC)
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ init_clk_usdhc(1);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_request(USDHC2_CD_GPIO, "SD_1_CD#");
+ gpio_direction_input(USDHC2_CD_GPIO);
+ break;
+ case 1:
+ init_clk_usdhc(2);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = 1; /* eMMC */
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ return ret;
+ }
+
+ return 1;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+
+ ret = power_pca9450b_init(I2C_PMIC);
+ if (ret)
+ printf("power init failed\n");
+ p = pmic_get("PCA9450");
+ pmic_probe(p);
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+
+ /*
+ * increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85v for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1c);
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
+ pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+
+ /* Kernel uses OD/OD freq for SoC */
+ /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */
+ pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+
+ /* set CONFIG2 to enable the I2C level translator */
+ pmic_reg_write(p, PCA9450_CONFIG2, 0x1);
+
+ return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* Adjust PMIC voltage to 1.0V for 800 MHz */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ /* PMIC initialization */
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ puts("resetting ...\n");
+
+ reset_cpu(WDOG1_BASE_ADDR);
+
+ return 0;
+}
diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
new file mode 100644
index 0000000000..f1d5f889b5
--- /dev/null
+++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <dwc3-uboot.h>
+#include <errno.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <spl.h>
+#include <usb.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+/* Verdin UART_3, Console/Debug UART */
+static iomux_v3_cfg_t const uart_pads[] = {
+ MX8MP_PAD_UART3_RXD__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX8MP_PAD_UART3_TXD__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const sleep_moci_pads[] = {
+ MX8MP_PAD_SAI3_RXC__GPIO4_IO29 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(2);
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+ int rc;
+ phys_addr_t ecc0_start = 0xb0000000;
+ phys_addr_t ecc1_start = 0x130000000;
+ phys_addr_t ecc2_start = 0x1b0000000;
+ size_t ecc_size = 0x10000000;
+
+ rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size);
+ if (rc < 0) {
+ printf("Could not create ecc0 reserved-memory node.\n");
+ return rc;
+ }
+
+ rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size);
+ if (rc < 0) {
+ printf("Could not create ecc1 reserved-memory node.\n");
+ return rc;
+ }
+
+ rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size);
+ if (rc < 0) {
+ printf("Could not create ecc2 reserved-memory node.\n");
+ return rc;
+ }
+#endif
+
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Enable RGMII TX clk output */
+ setbits_le32(&gpr->gpr[1], BIT(22));
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DWC_ETH_QOS
+static int setup_eqos(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+ setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS)
+int board_phy_config(struct phy_device *phydev)
+{
+ int tmp;
+
+ switch(ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
+ case PHY_ID_KSZ9031:
+ /*
+ * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by default. The MAC
+ * and the layout don't add a skew between clock and data.
+ * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for the TXC path
+ * to get the required clock skews.
+ */
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0070);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x7777);
+ /* tx data pad skew - devaddr = 0x02, register = 0x06 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03f4);
+ break;
+ case PHY_ID_KSZ9131:
+ default:
+ /* read rxc dll control - devaddr = 0x2, register = 0x4c */
+ tmp = ksz9031_phy_extended_read(phydev, 0x02,
+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC);
+ /* disable rxdll bypass (enable 2ns skew delay on RXC) */
+ tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+ /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
+ tmp = ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
+ /* read txc dll control - devaddr = 0x02, register = 0x4d */
+ tmp = ksz9031_phy_extended_read(phydev, 0x02,
+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC);
+ /* disable txdll bypass (enable 2ns skew delay on TXC) */
+ tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+ /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
+ tmp = ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
+ break;
+ }
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0 0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
+
+#define USB_PHY_CTRL1 0xF0044
+#define USB_PHY_CTRL1_RESET BIT(0)
+#define USB_PHY_CTRL1_COMMONONN BIT(1)
+#define USB_PHY_CTRL1_ATERESET BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
+
+#define USB_PHY_CTRL2 0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
+
+#define USB_PHY_CTRL6 0xF0058
+
+#define HSIO_GPR_BASE (0x32F10000U)
+#define HSIO_GPR_REG_0 (HSIO_GPR_BASE)
+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1)
+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT)
+
+static struct dwc3_device dwc3_device_data = {
+#ifdef CONFIG_SPL_BUILD
+ .maximum_speed = USB_SPEED_HIGH,
+#else
+ .maximum_speed = USB_SPEED_SUPER,
+#endif
+ .base = USB1_BASE_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+ .power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+ u32 RegData;
+
+ /* enable usb clock via hsio gpr */
+ RegData = readl(HSIO_GPR_REG_0);
+ RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN;
+ writel(RegData, HSIO_GPR_REG_0);
+
+ /* USB3.0 PHY signal fsel for 100M ref */
+ RegData = readl(dwc3->base + USB_PHY_CTRL0);
+ RegData = (RegData & 0xfffff81f) | (0x2a<<5);
+ writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL6);
+ RegData &=~0x1;
+ writel(RegData, dwc3->base + USB_PHY_CTRL6);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
+ RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+ USB_PHY_CTRL1_COMMONONN);
+ RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL0);
+ RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+ writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL2);
+ RegData |= USB_PHY_CTRL2_TXENABLEN0;
+ writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
+ RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+#define USB2_PWR_EN IMX_GPIO_NR(1, 14)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int ret = 0;
+ imx8m_usb_power(index, true);
+
+ if (index == 0 && init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_TCPC
+ ret = tcpc_setup_ufp_mode(&port1);
+ if (ret)
+ return ret;
+#endif
+ dwc3_nxp_usb_phy_init(&dwc3_device_data);
+ return dwc3_uboot_init(&dwc3_device_data);
+ } else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+ ret = tcpc_setup_dfp_mode(&port1);
+#endif
+ return ret;
+ } else if (index == 1 && init == USB_INIT_HOST) {
+ /* Enable GPIO1_IO14 for 5V VBUS */
+ gpio_request(USB2_PWR_EN, "usb2_pwr");
+ gpio_direction_output(USB2_PWR_EN, 1);
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ int ret = 0;
+ if (index == 0 && init == USB_INIT_DEVICE) {
+ dwc3_uboot_exit(index);
+ } else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+ ret = tcpc_disable_src_vbus(&port1);
+#endif
+ } else if (index == 1 && init == USB_INIT_HOST) {
+ /* Disable GPIO1_IO14 for 5V VBUS */
+ gpio_direction_output(USB2_PWR_EN, 0);
+ }
+
+ imx8m_usb_power(index, false);
+
+ return ret;
+}
+
+#endif
+
+#define FSL_SIP_GPC 0xC2000000
+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x3
+#define DISPMIX 13
+#define MIPI 15
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+#ifdef CONFIG_DWC_ETH_QOS
+ /* clock, pin, gpr */
+ setup_eqos();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+ init_usb_clk();
+#endif
+
+ return 0;
+}
+
+static void select_dt_from_module_version(void)
+{
+ char variant[32];
+ char *env_variant = env_get("variant");
+ int is_wifi = 0;
+
+#ifdef CONFIG_TDX_CFG_BLOCK
+ /*
+ * If we have a valid config block and it says we are a module with
+ * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
+ */
+ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT);
+#endif
+
+ if (is_wifi)
+ strncpy(&variant[0], "wifi", sizeof(variant));
+ else
+ strncpy(&variant[0], "nonwifi", sizeof(variant));
+
+ if (strcmp(variant, env_variant)) {
+ printf("Setting variant to %s\n", variant);
+ env_set("variant", variant);
+#ifndef CONFIG_ENV_IS_NOWHERE
+ env_save();
+#endif
+ }
+}
+
+int board_late_init(void)
+{
+ select_dt_from_module_version();
+
+ /* Power up carrier board HW, e.g. USB */
+ imx_iomux_v3_setup_multiple_pads(sleep_moci_pads, ARRAY_SIZE(sleep_moci_pads));
+ gpio_request(IMX_GPIO_NR(4, 29), "SLEEP_MOCI#");
+ gpio_direction_output(IMX_GPIO_NR(4, 29), 1);
+
+ return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *bank1_size, phys_size_t *bank2_size)
+{
+ if (!bank1_size || !bank2_size)
+ return -EINVAL;
+
+ /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
+ *bank1_size = get_ram_size((long *)PHYS_SDRAM, 0x200000000);
+
+ if (*bank1_size > PHYS_SDRAM_SIZE) {
+ *bank2_size = *bank1_size - PHYS_SDRAM_SIZE;
+ *bank1_size = PHYS_SDRAM_SIZE;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+ return 0; /* TODO */
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+ return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
+}
+#endif
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+#define UBOOT_RAW_SECTOR_OFFSET 0x40
+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
+{
+ u32 boot_dev = spl_boot_device();
+ switch (boot_dev) {
+ case BOOT_DEVICE_MMC2:
+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
+ default:
+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+ }
+}
+#endif
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
new file mode 100644
index 0000000000..232185e2c3
--- /dev/null
+++ b/configs/verdin-imx8mp_defconfig
@@ -0,0 +1,124 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+# SPL fails if bigger
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_ENV_SIZE=0x2000
+# Bogus, gets overwritten in include/configs/verdin-imx8mp.h
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_VERDIN_IMX8MP=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/verdin-imx8mp/imximage.cfg"
+CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdtfile imx8mp-verdin-${variant}-${fdt_board}.dtb"
+CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_PROMPT="Verdin iMX8MP # "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-verdin"
+# SPL recovery crashes otherwise
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
new file mode 100644
index 0000000000..be0cca95d5
--- /dev/null
+++ b/include/configs/verdin-imx8mp.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Toradex
+ */
+
+#ifndef __VERDIN_IMX8MP_H
+#define __VERDIN_IMX8MP_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#include "imx_env.h"
+
+#define CONFIG_SPL_MAX_SIZE (152 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x187FF0
+#define CONFIG_SPL_BSS_START_ADDR 0x0095e000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+
+#define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PCA9450
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 3
+#define FEC_QUIRK_ENET_MAC
+
+#define DWC_NET_PHYADDR 7
+#ifdef CONFIG_DWC_ETH_QOS
+#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
+#endif
+
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif /* CONFIG_CMD_NET */
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x43000000\0" \
+ "kernel_addr_r=0x40000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "scriptaddr=0x46000000\0"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x43500000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Enable Distro Boot */
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(USB, usb, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef CONFIG_ISO_PARTITION
+#else
+#define BOOTENV
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "bootcmd_mfg=fastboot 0\0" \
+ "console=ttymxc2\0" \
+ "fdt_board=dev\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "boot_script_dhcp=boot.scr\0" \
+ "boot_file=Image\0" \
+ "setup=setenv setupargs console=${console},${baudrate} console=tty1 consoleblank=0 earlycon\0"
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_ENV_OFFSET
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
+ CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV 2
+#define CONFIG_SYS_MMC_ENV_PART 1
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+
+/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE 0x140000000 /* 5 GB */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#endif /* __VERDIN_IMX8MP_H */
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-19 20:43:29 +0000