diff options
| author | Bryan Brattlof <bb@ti.com> | 2024-02-21 14:07:04 -0600 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2024-03-21 14:26:33 +0000 |
| commit | 0737aa808c22590f9cd78797aa83b974c6f8e071 (patch) | |
| tree | 55420ffffd89ec7deca85154cb005d4047b3d178 | |
| parent | c8f34655fdabcc8252cb24fb5f11704403981038 (diff) | |
arm: dts: k3-am62x-sip-lp4: update to latest emif output
Nothing much has changed between the versions of the emif output. Some
changes to the PHY_PAD_CAL_IO_CFG_0, PHY PAD RST DRIVE, and
PHY_CAL_CLK_SELECT_0 should add some minor stability improvements.
Nonetheless, update to the latest characterization developments.
Signed-off-by: Bryan Brattlof <bb@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi b/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi index 04c9a78fba..61894ee3ae 100644 --- a/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi +++ b/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.03 - * Mon Nov 21 2022 09:04:01 GMT-0600 (Central Standard Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10 + * Mon Oct 16 2023 09:44:16 GMT-0500 (Central Daylight Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 4Gb @@ -827,7 +827,7 @@ #define DDRSS_PHY_41_DATA 0x00005555 #define DDRSS_PHY_42_DATA 0x01000100 #define DDRSS_PHY_43_DATA 0x00800180 -#define DDRSS_PHY_44_DATA 0x00000000 // [SWAP] PHY_CALVL_VREF_DRIVING_SLICE_0 //0x00000001 Normal +#define DDRSS_PHY_44_DATA 0x00000000 #define DDRSS_PHY_45_DATA 0x00000000 #define DDRSS_PHY_46_DATA 0x00000000 #define DDRSS_PHY_47_DATA 0x00000000 @@ -886,7 +886,7 @@ #define DDRSS_PHY_100_DATA 0x000001CC #define DDRSS_PHY_101_DATA 0x20100200 #define DDRSS_PHY_102_DATA 0x00000005 -#define DDRSS_PHY_103_DATA 0x56743210 // [SWIZZLE] PHY_DQ_DM_SWIZZLE0_0 //0x76543210 Swizzle DV +#define DDRSS_PHY_103_DATA 0x56743210 #define DDRSS_PHY_104_DATA 0x00000008 #define DDRSS_PHY_105_DATA 0x034C034C #define DDRSS_PHY_106_DATA 0x034C034C @@ -1083,7 +1083,7 @@ #define DDRSS_PHY_297_DATA 0x00005555 #define DDRSS_PHY_298_DATA 0x01000100 #define DDRSS_PHY_299_DATA 0x00800180 -#define DDRSS_PHY_300_DATA 0x00000001 // [SWAP] PHY_CALVL_VREF_DRIVING_SLICE_1 //0x00000000 Normal +#define DDRSS_PHY_300_DATA 0x00000001 #define DDRSS_PHY_301_DATA 0x00000000 #define DDRSS_PHY_302_DATA 0x00000000 #define DDRSS_PHY_303_DATA 0x00000000 @@ -1142,7 +1142,7 @@ #define DDRSS_PHY_356_DATA 0x000001CC #define DDRSS_PHY_357_DATA 0x20100200 #define DDRSS_PHY_358_DATA 0x00000005 -#define DDRSS_PHY_359_DATA 0x01324567 // [SWIZZLE] PHY_DQ_DM_SWIZZLE0_1 //0x76543210 //Normal +#define DDRSS_PHY_359_DATA 0x01324567 #define DDRSS_PHY_360_DATA 0x00000008 #define DDRSS_PHY_361_DATA 0x034C034C #define DDRSS_PHY_362_DATA 0x034C034C @@ -2142,7 +2142,7 @@ #define DDRSS_PHY_1356_DATA 0x00000000 #define DDRSS_PHY_1357_DATA 0x00000000 #define DDRSS_PHY_1358_DATA 0x00000000 -#define DDRSS_PHY_1359_DATA 0x76543201 // [SWAP] PHY_DATA_BYTE_ORDER_SEL //0x76543210 //Normal +#define DDRSS_PHY_1359_DATA 0x76543201 #define DDRSS_PHY_1360_DATA 0x00040198 #define DDRSS_PHY_1361_DATA 0x00000000 #define DDRSS_PHY_1362_DATA 0x00000000 @@ -2154,7 +2154,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000000 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x00000AC3 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 @@ -2182,10 +2182,10 @@ #define DDRSS_PHY_1396_DATA 0x0089FF00 #define DDRSS_PHY_1397_DATA 0x000C3F11 #define DDRSS_PHY_1398_DATA 0x01990000 -#define DDRSS_PHY_1399_DATA 0x000C3F11 +#define DDRSS_PHY_1399_DATA 0x000C3F91 #define DDRSS_PHY_1400_DATA 0x01990000 #define DDRSS_PHY_1401_DATA 0x3F0DFF11 #define DDRSS_PHY_1402_DATA 0x01990000 #define DDRSS_PHY_1403_DATA 0x00018011 #define DDRSS_PHY_1404_DATA 0x0089FF00 -#define DDRSS_PHY_1405_DATA 0x20040002 +#define DDRSS_PHY_1405_DATA 0x20040004 |