diff options
| author | Ye Li <ye.li@nxp.com> | 2022-05-06 15:04:26 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-07-06 22:36:03 +0800 |
| commit | 1c061790f53674830101ab42fc420dd0a730669e (patch) | |
| tree | 47f356e55b81b1b8daf70e401aff83cc6eefddc5 | |
| parent | 28397a7d35f7c2d2275058295d8017ad3e787a4c (diff) | |
LFU-330-42 ddr: imx9: enable Performance monitor counter
Add Kconfig for enabling reference events counter in DDRC performance
monitor by default
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | arch/arm/include/asm/arch-imx9/ddr.h | 1 | ||||
| -rw-r--r-- | drivers/ddr/imx/imx9/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/ddr/imx/imx9/ddr_init.c | 4 |
3 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index fa11133c3d..38a2033f0d 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -15,6 +15,7 @@ #define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) +#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48) #define SRC_BASE_ADDR (0x44460000) #define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400) diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index a16ddc65e0..123ad173cf 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -11,6 +11,12 @@ config IMX9_LPDDR4X help Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC. +config IMX9_DRAM_PM_COUNTER + bool "imx9 DDRC performance monitor counter" + default y + help + Enable DDR controller performance monitor counter for reference events. + config SAVED_DRAM_TIMING_BASE hex "Define the base address for saved dram timing" help diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index c6900eadce..56032df7e0 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -111,6 +111,10 @@ int ddr_init(struct dram_timing_info *dram_timing) ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); debug("DDRINFO: ddrc config done\n"); +#ifdef CONFIG_IMX9_DRAM_PM_COUNTER + writel(0x200000, REG_DDR_DEBUG_19); +#endif + check_dfi_init_complete(); regval=readl(REG_DDR_SDRAM_CFG); |