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authorPhilippe Schenker <philippe.schenker@toradex.com>2020-03-04 19:33:47 +0100
committerIgor Opaniuk <igor.opaniuk@toradex.com>2020-08-05 19:26:24 +0300
commit4bc270e862a12707e30864c50444c943ada5d164 (patch)
treeccc7730bc98a22a950623d872c8ca441ab61d8e7
parentb4fc2b1de85765f2a2184042e11d2503cc4d4f40 (diff)
board: verdin-imx8mm: Add KSZ9131 phy skew settings
This patch basically just enables both RXC and TXC delay lines in the PHY. This will compensate the missing delay from the MAC. Other skew settings are not needed as the traces on board are routed exactly the same length Related-to: ELB-1299 Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> (cherry picked from commit 50e975e6ce4e4e88f8c5c943ef2ddc38b0a31997) (cherry picked from commit f65442d8224dea0068a3d23db139608920688291)
-rw-r--r--board/toradex/verdin-imx8mm/verdin-imx8mm.c73
-rw-r--r--include/micrel.h9
2 files changed, 60 insertions, 22 deletions
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index b7705be4ed..95fd1a2999 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -86,28 +86,57 @@ static int setup_fec(void)
int board_phy_config(struct phy_device *phydev)
{
-/*
- * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by default. The MAC
- * and the layout don't add a skew between clock and data.
- * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for the TXC path
- * to get the required clock skews.
- */
- /* control data pad skew - devaddr = 0x02, register = 0x04 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0070);
- /* rx data pad skew - devaddr = 0x02, register = 0x05 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x7777);
- /* tx data pad skew - devaddr = 0x02, register = 0x06 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
- /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03f4);
+ int tmp;
+
+ switch(ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
+ case PHY_ID_KSZ9031:
+ /*
+ * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by default. The MAC
+ * and the layout don't add a skew between clock and data.
+ * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for the TXC path
+ * to get the required clock skews.
+ */
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0070);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x7777);
+ /* tx data pad skew - devaddr = 0x02, register = 0x06 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03f4);
+ break;
+ case PHY_ID_KSZ9131:
+ default:
+ /* read rxc dll control - devaddr = 0x2, register = 0x4c */
+ tmp = ksz9031_phy_extended_read(phydev, 0x02,
+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC);
+ /* disable rxdll bypass (enable 2ns skew delay on RXC) */
+ tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+ /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
+ tmp = ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
+ /* read txc dll control - devaddr = 0x02, register = 0x4d */
+ tmp = ksz9031_phy_extended_read(phydev, 0x02,
+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC);
+ /* disable txdll bypass (enable 2ns skew delay on TXC) */
+ tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+ /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
+ tmp = ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
+ break;
+ }
if (phydev->drv->config)
phydev->drv->config(phydev);
diff --git a/include/micrel.h b/include/micrel.h
index 3e6b5312d8..01ec879226 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -23,6 +23,15 @@
#define MII_KSZ9031_FLP_BURST_TX_LO 0x3
#define MII_KSZ9031_FLP_BURST_TX_HI 0x4
+#define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0
+
+#define MII_KSZ9131_RXTXDLL_BYPASS BIT(12)
+#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL 0x4c
+#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL 0x4d
+
+#define PHY_ID_KSZ9031 0x00221620
+#define PHY_ID_KSZ9131 0x00221640
+
/* Registers */
#define MMD_ACCESS_CONTROL 0xd
#define MMD_ACCESS_REG_DATA 0xe