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authorMichal Simek <michal.simek@xilinx.com>2014-07-16 10:43:47 +0200
committerMichal Simek <michal.simek@xilinx.com>2015-01-21 10:25:02 +0100
commit4e9acc16fc026ae0991b32e52c15c0e9a36a53a7 (patch)
treedc30905fc740af5b84848572d42c76d8c5c6b042
parentebd322de43d7d43dd59955aa58952bafa95cfd4a (diff)
fpga: xilinx: spartan2: Setup NULL fpga_op without driver
Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--include/spartan2.h38
1 files changed, 27 insertions, 11 deletions
diff --git a/include/spartan2.h b/include/spartan2.h
index 2aca954e73..14606c3031 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -38,7 +38,12 @@ typedef struct {
xilinx_post_fn post;
} xilinx_spartan2_slave_serial_fns;
+#if defined(CONFIG_FPGA_SPARTAN2)
extern struct xilinx_fpga_op spartan2_op;
+# define FPGA_SPARTAN2_OPS &spartan2_op
+#else
+# define FPGA_SPARTAN2_OPS NULL
+#endif
/* Device Image Sizes
*********************************************************************/
@@ -61,36 +66,47 @@ extern struct xilinx_fpga_op spartan2_op;
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#endif /* _SPARTAN2_H_ */