diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2019-04-02 20:41:23 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-05-08 17:34:12 +0800 |
| commit | 5793e8c271f73da2ca50fa3d57d3fea7e3d2796c (patch) | |
| tree | 83dbf49c8756a857bbe557980544d924fc94483b | |
| parent | e4d0d61275ac1b14375be8f62585398e05b19f3f (diff) | |
rockchip: clk: rk322x: fix assert clock value
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk322x.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4b599fbb24..f09730c91b 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -121,10 +121,10 @@ static void rkclk_init(struct rk322x_cru *cru) assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; - assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); + assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7); hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; - assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); + assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3); rk_clrsetreg(&cru->cru_clksel_con[0], BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, |