MA-19048-1 MCU security enhancement

Move the MCU RDC config to dts, it will be parsed by
SPL and stored in OCRAM_S, then the MCU RDC config will
be setup before MCU kicking.

Use HAB to verify the MCU image to guarantee its integrity.

Change-Id: I82dd378a6516b4d3cc47c5de2e403d817ba80256
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 2e972e4aa6c44eec0444d59d11c0a0c175699cf2)

13 files changed, 574 insertions, 17 deletions

diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts b/arch/arm/dts/imx8mn-ddr3l-evk.dts
index acf6b2ff2b..aec6fe4e73 100644
--- a/arch/arm/dts/imx8mn-ddr3l-evk.dts
+++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts
@@ -5,8 +5,50 @@
 
 #include "imx8mn-evk.dts"
 
+#include "imx8mn-sec-def.h"
+
 / {
 	model = "NXP i.MX8MNano DDR3L EVK board";
+
+	mcu_rdc {
+		compatible = "imx8m,mcu_rdc";
+			    /* rdc config when MCU starts
+			     * master
+			     *   SDMA3p --> domain 1
+			     *   SDMA3b --> domian 1
+			     *   SDMA3_SPBA2  --> domian 1
+			     * peripheral:
+			     *   SAI3   --> Only Domian 1 can access
+			     *   UART4  --> Only Domian 1 can access
+			     *   GPT1   --> Only Domian 1 can access
+			     * memory:
+			     *   TCM    --> Only Domian 1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> Only Domian 1 can access (0x77000000~0x78000000)
+			     * end.
+			     */
+		start-config = <
+			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR3L_START M4_EVK_DDR3L_END MEM_D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+			    /* rdc config when MCU stops
+			     * memory:
+			     *   TCM    --> domain 0/1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> domain 0/1 can access (0x77000000~0x78000000)
+			     * end.
+			     */
+		stop-config = <
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D0D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR3L_START M4_EVK_DDR3L_END MEM_D0D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+	};
 };
 
 &dsi_host {
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index e817275f59..89740a6d99 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -3,6 +3,8 @@
  * Copyright 2019, 2021 NXP
  */
 
+#include "imx8mn-sec-def.h"
+
 / {
 	binman: binman {
 		multiple-images;
@@ -31,6 +33,46 @@
 			method = "smc";
 		};
 	};
+
+	mcu_rdc {
+		compatible = "imx8m,mcu_rdc";
+			    /* rdc config when MCU starts
+			     * master
+			     *   SDMA3p --> domain 1
+			     *   SDMA3b --> domian 1
+			     *   SDMA3_SPBA2  --> domian 1
+			     * peripheral:
+			     *   SAI3   --> Only Domian 1 can access
+			     *   UART4  --> Only Domian 1 can access
+			     *   GPT1   --> Only Domian 1 can access
+			     * memory:
+			     *   TCM    --> Only Domian 1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> Only Domian 1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		start-config = <
+			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR4_START M4_EVK_DDR4_END MEM_D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+			    /* rdc config when MCU stops
+			     * memory:
+			     *   TCM    --> domain 0/1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> domain 0/1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		stop-config = <
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D0D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR4_START M4_EVK_DDR4_END MEM_D0D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+	};
 };
 
 &{/soc@0} {
diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
index f7dd85e356..f92c0f586f 100644
--- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
@@ -3,6 +3,8 @@
  * Copyright 2019 NXP
  */
 
+#include "imx8mn-sec-def.h"
+
 / {
 	binman: binman {
 		multiple-images;
@@ -31,6 +33,45 @@
 			method = "smc";
 		};
 	};
+	mcu_rdc {
+		compatible = "imx8m,mcu_rdc";
+			    /* rdc config when MCU starts
+			     * master
+			     *   SDMA3p --> domain 1
+			     *   SDMA3b --> domian 1
+			     *   SDMA3_SPBA2  --> domian 1
+			     * peripheral:
+			     *   SAI3   --> Only Domian 1 can access
+			     *   UART4  --> Only Domian 1 can access
+			     *   GPT1   --> Only Domian 1 can access
+			     * memory:
+			     *   TCM    --> Only Domian 1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> Only Domian 1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		start-config = <
+			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR4_START M4_EVK_DDR4_END MEM_D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+			    /* rdc config when MCU stops
+			     * memory:
+			     *   TCM    --> domain 0/1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> domain 0/1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		stop-config = <
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D0D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR4_START M4_EVK_DDR4_END MEM_D0D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+	};
 };
 
 &{/soc@0} {
diff --git a/arch/arm/dts/imx8mn-sec-def.h b/arch/arm/dts/imx8mn-sec-def.h
new file mode 100644
index 0000000000..03a16ada67
--- /dev/null
+++ b/arch/arm/dts/imx8mn-sec-def.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef IMX8MN_SEC_DEF_H
+#define IMX8MN_SEC_DEF_H
+
+/* Domain ID */
+#define DID0            0x0
+#define DID1            0x1
+#define DID2            0x2
+#define DID3            0x3
+
+/* Domain RD/WR permission */
+#define LOCK           0x80000000
+#define ENA            0x40000000
+#define D3R            0x00000080
+#define D3W            0x00000040
+#define D2R            0x00000020
+#define D2W            0x00000010
+#define D1R            0x00000008
+#define D1W            0x00000004
+#define D0R            0x00000002
+#define D0W            0x00000001
+
+#define PDAP_D1_ACCESS 0x0000000C /* D1W|D1R */
+#define MEM_D1_ACCESS  0x4000000C /* ENA|D1W|D1R */
+#define MEM_D0D1_ACCESS  0x4000000F /* ENA|D0W|D0R|D1W|D1R */
+
+/* RDC type */
+#define RDC_INVALID 0
+#define RDC_MDA 1
+#define RDC_PDAP 2
+#define RDC_MEM_REGION 3
+
+/* RDC MDA index */
+#define RDC_MDA_A53  0
+#define RDC_MDA_M7  1
+#define RDC_MDA_SDMA3p  3
+#define RDC_MDA_LCDIF1  5
+#define RDC_MDA_ISI  6
+#define RDC_MDA_SDMA3b  7
+#define RDC_MDA_Coresight  8
+#define RDC_MDA_DAP  9
+#define RDC_MDA_CAAM  10
+#define RDC_MDA_SDMA1p  11
+#define RDC_MDA_SDMA1b  12
+#define RDC_MDA_APBHDMA  13
+#define RDC_MDA_RAWNAND  14
+#define RDC_MDA_uSDHC1  15
+#define RDC_MDA_uSDHC2  16
+#define RDC_MDA_uSDHC3  17
+#define RDC_MDA_GPU  18
+#define RDC_MDA_USB1 19
+#define RDC_MDA_TESTPORT 21
+#define RDC_MDA_ENET1_TX 22
+#define RDC_MDA_ENET1_RX 23
+#define RDC_MDA_SDMA2 24
+#define RDC_MDA_SDMA3_SPBA2 25
+
+/* RDC Peripherals index */
+#define RDC_PDAP_GPIO1  0
+#define RDC_PDAP_GPIO2  1
+#define RDC_PDAP_GPIO3  2
+#define RDC_PDAP_GPIO4  3
+#define RDC_PDAP_GPIO5  4
+#define RDC_PDAP_ANA_TSENSOR  6
+#define RDC_PDAP_ANA_OSC  7
+#define RDC_PDAP_WDOG1  8
+#define RDC_PDAP_WDOG2  9
+#define RDC_PDAP_WDOG3  10
+#define RDC_PDAP_SDMA2  12
+#define RDC_PDAP_GPT1  13
+#define RDC_PDAP_GPT2  14
+#define RDC_PDAP_GPT3  15
+#define RDC_PDAP_ROMCP  17
+#define RDC_PDAP_IOMUXC  19
+#define RDC_PDAP_IOMUXC_GPR  20
+#define RDC_PDAP_OCOTP_CTRL  21
+#define RDC_PDAP_ANA_PLL  22
+#define RDC_PDAP_SNVS_HP  23
+#define RDC_PDAP_CCM  24
+#define RDC_PDAP_SRC  25
+#define RDC_PDAP_GPC  26
+#define RDC_PDAP_SEMAPHORE1  27
+#define RDC_PDAP_SEMAPHORE2  28
+#define RDC_PDAP_RDC  29
+#define RDC_PDAP_CSU  30
+#define RDC_PDAP_LCDIF  32
+#define RDC_PDAP_MIPI_DSI  33
+#define RDC_PDAP_ISI  34
+#define RDC_PDAP_MIPI_CSI  35
+#define RDC_PDAP_USB1  36
+#define RDC_PDAP_PWM1  38
+#define RDC_PDAP_PWM2  39
+#define RDC_PDAP_PWM3  40
+#define RDC_PDAP_PWM4  41
+#define RDC_PDAP_System_Counter_RD  42
+#define RDC_PDAP_System_Counter_CMP  43
+#define RDC_PDAP_System_Counter_CTRL  44
+#define RDC_PDAP_GPT6  46
+#define RDC_PDAP_GPT5  47
+#define RDC_PDAP_GPT4  48
+#define RDC_PDAP_TZASC  56
+#define RDC_PDAP_PERFMON1  60
+#define RDC_PDAP_PERFMON2  61
+#define RDC_PDAP_PLATFORM_CTRL  62
+#define RDC_PDAP_QoSC  63
+#define RDC_PDAP_I2C1  66
+#define RDC_PDAP_I2C2  67
+#define RDC_PDAP_I2C3  68
+#define RDC_PDAP_I2C4  69
+#define RDC_PDAP_UART4  70
+#define RDC_PDAP_MU_A  74
+#define RDC_PDAP_MU_B  75
+#define RDC_PDAP_SEMAPHORE_HS  76
+#define RDC_PDAP_SAI2  79
+#define RDC_PDAP_SAI3  80
+#define RDC_PDAP_SAI5  82
+#define RDC_PDAP_SAI6  83
+#define RDC_PDAP_uSDHC1  84
+#define RDC_PDAP_uSDHC2  85
+#define RDC_PDAP_uSDHC3  86
+#define RDC_PDAP_SAI7  87
+#define RDC_PDAP_SPBA2  90
+#define RDC_PDAP_QSPI  91
+#define RDC_PDAP_SDMA1  93
+#define RDC_PDAP_ENET1  94
+#define RDC_PDAP_SPDIF1  97
+#define RDC_PDAP_eCSPI1  98
+#define RDC_PDAP_eCSPI2  99
+#define RDC_PDAP_eCSPI3  100
+#define RDC_PDAP_MICFIL  101
+#define RDC_PDAP_UART1  102
+#define RDC_PDAP_UART3  104
+#define RDC_PDAP_UART2  105
+#define RDC_PDAP_ASRC  107
+#define RDC_PDAP_SPBA1  111
+#define RDC_PDAP_CAAM  114
+
+/* RDC MEMORY REGION */
+#define TCM_START 0x7E0000
+#define TCM_END   0x820000
+
+#define M4_EVK_DDR4_START 0x20000000
+#define M4_EVK_DDR4_END 0x20800000
+
+#define M4_EVK_DDR3L_START 0x1B800000
+#define M4_EVK_DDR3L_END 0x1C000000
+
+#endif /* IMX8MN_SEC_DEF_H */
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index d470195e25..16d98cb659 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -2,6 +2,7 @@
 /*
  * Copyright 2019, 2021 NXP
  */
+#include "imx8mp-sec-def.h"
 
 #include "imx8mp-u-boot.dtsi"
 
@@ -17,6 +18,50 @@
 			method = "smc";
 		};
 	};
+
+	mcu_rdc {
+		compatible = "imx8m,mcu_rdc";
+			    /* rdc config when MCU starts
+			     * master
+			     *   SDMA3p --> domain 1
+			     *   SDMA3b --> domian 1
+			     *   SDMA3_SPBA2  --> domian 1
+			     * peripheral:
+			     *   SAI3   --> Only Domian 1 can access
+			     *   UART4  --> Only Domian 1 can access
+			     *   GPT1   --> Only Domian 1 can access
+			     *   SDMA3  --> Only Domian 1 can access
+			     *   I2C3   --> Only Domian 1 can access
+			     * memory:
+			     *   TCM    --> Only Domian 1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> Only Domian 1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		start-config = <
+			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_I2C3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS
+			    RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+			    /* rdc config when MCU stops
+			     * memory:
+			     *   TCM    --> domain 0/1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> domain 0/1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		stop-config = <
+			    RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS
+			    RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+	};
 };
 
 &pinctrl_reg_usdhc2_vmmc {
diff --git a/arch/arm/dts/imx8mp-sec-def.h b/arch/arm/dts/imx8mp-sec-def.h
new file mode 100644
index 0000000000..420e584bff
--- /dev/null
+++ b/arch/arm/dts/imx8mp-sec-def.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef IMX8MP_SEC_DEF_H
+#define IMX8MP_SEC_DEF_H
+
+/* Domain ID */
+#define DID0            0x0
+#define DID1            0x1
+#define DID2            0x2
+#define DID3            0x3
+
+/* Domain RD/WR permission */
+#define LOCK           0x80000000
+#define ENA            0x40000000
+#define D3R            0x00000080
+#define D3W            0x00000040
+#define D2R            0x00000020
+#define D2W            0x00000010
+#define D1R            0x00000008
+#define D1W            0x00000004
+#define D0R            0x00000002
+#define D0W            0x00000001
+
+#define PDAP_D1_ACCESS 0x0000000C /* D1W|D1R */
+#define MEM_D1_ACCESS  0x4000000C /* ENA|D1W|D1R */
+#define MEM_D0D1_ACCESS  0x4000000F /* ENA|D0W|D0R|D1W|D1R */
+
+/* RDC type */
+#define RDC_INVALID 0
+#define RDC_MDA 1
+#define RDC_PDAP 2
+#define RDC_MEM_REGION 3
+
+/* RDC MDA index */
+#define RDC_MDA_A53  0
+#define RDC_MDA_M7  1
+#define RDC_MDA_SDMA3p  3
+#define RDC_MDA_SDMA3b  4
+#define RDC_MDA_LCDIF1  5
+#define RDC_MDA_ISI  6
+#define RDC_MDdA_NPU = 7
+#define RDC_MDA_Coresight  8
+#define RDC_MDA_DAP  9
+#define RDC_MDA_CAAM  10
+#define RDC_MDA_SDMA1p  11
+#define RDC_MDA_SDMA1b  12
+#define RDC_MDA_APBHDMA  13
+#define RDC_MDA_RAWNAND  14
+#define RDC_MDA_uSDHC1  15
+#define RDC_MDA_uSDHC2  16
+#define RDC_MDA_uSDHC3  17
+#define RDC_MDA_SDMA3_SPBA2 25
+#define RDC_MDA_LCDIF2  27
+#define RDC_MDA_HDMI_TX  28
+#define RDC_MDA_GPU3D  30
+#define RDC_MDA_GPU2D  31
+#define RDC_MDA_VPUG1  32
+#define RDC_MDA_VPUG2  33
+#define RDC_MDA_VC8000E  34
+
+/* RDC Peripherals index */
+#define RDC_PDAP_GPIO1  0
+#define RDC_PDAP_GPIO2  1
+#define RDC_PDAP_GPIO3  2
+#define RDC_PDAP_GPIO4  3
+#define RDC_PDAP_GPIO5  4
+#define RDC_PDAP_ANA_TSENSOR  6
+#define RDC_PDAP_ANA_OSC  7
+#define RDC_PDAP_WDOG1  8
+#define RDC_PDAP_WDOG2  9
+#define RDC_PDAP_WDOG3  10
+#define RDC_PDAP_SDMA2  12
+#define RDC_PDAP_GPT1  13
+#define RDC_PDAP_GPT2  14
+#define RDC_PDAP_GPT3  15
+#define RDC_PDAP_ROMCP  17
+#define RDC_PDAP_IOMUXC  19
+#define RDC_PDAP_IOMUXC_GPR  20
+#define RDC_PDAP_OCOTP_CTRL  21
+#define RDC_PDAP_ANA_PLL  22
+#define RDC_PDAP_SNVS_HP  23
+#define RDC_PDAP_CCM  24
+#define RDC_PDAP_SRC  25
+#define RDC_PDAP_GPC  26
+#define RDC_PDAP_SEMAPHORE1  27
+#define RDC_PDAP_SEMAPHORE2  28
+#define RDC_PDAP_RDC  29
+#define RDC_PDAP_CSU  30
+#define RDC_PDAP_LCDIF  32
+#define RDC_PDAP_MIPI_DSI  33
+#define RDC_PDAP_ISI  34
+#define RDC_PDAP_MIPI_CSI  35
+#define RDC_PDAP_USB1  36
+#define RDC_PDAP_PWM1  38
+#define RDC_PDAP_PWM2  39
+#define RDC_PDAP_PWM3  40
+#define RDC_PDAP_PWM4  41
+#define RDC_PDAP_System_Counter_RD  42
+#define RDC_PDAP_System_Counter_CMP  43
+#define RDC_PDAP_System_Counter_CTRL  44
+#define RDC_PDAP_GPT6  46
+#define RDC_PDAP_GPT5  47
+#define RDC_PDAP_GPT4  48
+#define RDC_PDAP_TZASC  56
+#define RDC_PDAP_PERFMON1  60
+#define RDC_PDAP_PERFMON2  61
+#define RDC_PDAP_PLATFORM_CTRL  62
+#define RDC_PDAP_QoSC  63
+#define RDC_PDAP_I2C1  66
+#define RDC_PDAP_I2C2  67
+#define RDC_PDAP_I2C3  68
+#define RDC_PDAP_I2C4  69
+#define RDC_PDAP_UART4  70
+#define RDC_PDAP_MU_A  74
+#define RDC_PDAP_MU_B  75
+#define RDC_PDAP_SEMAPHORE_HS  76
+#define RDC_PDAP_SAI2  79
+#define RDC_PDAP_SAI3  80
+#define RDC_PDAP_SAI5  82
+#define RDC_PDAP_SAI6  83
+#define RDC_PDAP_uSDHC1  84
+#define RDC_PDAP_uSDHC2  85
+#define RDC_PDAP_uSDHC3  86
+#define RDC_PDAP_SAI7  87
+#define RDC_PDAP_SPBA2  90
+#define RDC_PDAP_QSPI  91
+#define RDC_PDAP_SDMA1  93
+#define RDC_PDAP_ENET1  94
+#define RDC_PDAP_SPDIF1  97
+#define RDC_PDAP_eCSPI1  98
+#define RDC_PDAP_eCSPI2  99
+#define RDC_PDAP_eCSPI3  100
+#define RDC_PDAP_MICFIL  101
+#define RDC_PDAP_UART1  102
+#define RDC_PDAP_UART3  104
+#define RDC_PDAP_UART2  105
+#define RDC_PDAP_ASRC  107
+#define RDC_PDAP_SDMA3  109
+#define RDC_PDAP_SPBA1  111
+#define RDC_PDAP_CAAM  114
+
+/* RDC MEMORY REGION */
+#define TCM_START 0x7E0000
+#define TCM_END   0x820000
+#define M4_DDR_START 0x20000000
+#define M4_DDR_END 0x20800000
+
+#endif /* IMX8MP_SEC_DEF_H */
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index e6252b6ec7..456073873d 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -46,6 +46,14 @@ config IMX_UNIQUE_ID
 	depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP
 	default 0x0
 
+config IMX8M_MCU_RDC_START_CONFIG_ADDR
+	hex "Start address of mcu rdc config when mcu starts"
+	default 0x186000
+
+config IMX8M_MCU_RDC_STOP_CONFIG_ADDR
+	hex "Start address of mcu rdc config when mcu stops"
+	default 0x187000
+
 choice
 	prompt "NXP i.MX8M board select"
 	optional
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index dbf6e9ce95..682a7880c9 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -122,6 +122,14 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
 
 	/* Enable MCU */
 #ifdef CONFIG_IMX8M
+#if defined(CONFIG_IMX_HAB) && defined(CONFIG_ANDROID_SUPPORT)
+	extern int authenticate_image(
+		uint32_t ddr_start, uint32_t raw_image_size);
+	if (authenticate_image(addr, ANDROID_MCU_FIRMWARE_SIZE) != 0) {
+		printf("Authenticate MCU Image Fail, Please check.\n");
+		return -EINVAL;
+	}
+#endif
 	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0,
 		      0, 0, 0, 0, NULL);
 #else
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index bb3487bf23..2995ba4281 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -319,16 +319,6 @@ ulong board_spl_fit_size_align(ulong size)
 	return size;
 }
 
-void board_spl_fit_post_load(const void *fit)
-{
-	u32 offset = ALIGN(fdt_totalsize(fit), 0x1000);
-
-	if (imx_hab_authenticate_image((uintptr_t)fit,
-				       offset + IVT_SIZE + CSF_PAD_SIZE,
-				       offset)) {
-		panic("spl: ERROR:  image authentication unsuccessful\n");
-	}
-}
 #endif
 
 void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
@@ -390,6 +380,83 @@ void *spl_load_simple_fit_fix_load(const void *fit)
 	return (void *)new;
 }
 
+#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MN)
+int board_handle_rdc_config(void *fdt_addr, const char *config_name, void *dst_addr)
+{
+	int node = -1, size = 0, ret = 0;
+	uint32_t *data = NULL;
+	const struct fdt_property *prop;
+
+	node = fdt_node_offset_by_compatible(fdt_addr, -1, "imx8m,mcu_rdc");
+	if (node < 0) {
+		printf("Failed to find node!, err: %d!\n", node);
+		ret = -1;
+		goto exit;
+	}
+
+	/*
+	 * Before MCU core starts we should set the rdc config for it,
+	 * then restore the rdc config after it stops.
+	 */
+	prop = fdt_getprop(fdt_addr, node, config_name, &size);
+	if (!prop) {
+		printf("Failed to find property %s!\n", config_name);
+		ret = -1;
+		goto exit;
+	}
+	if (!size || size % (5 * sizeof(uint32_t))) {
+		printf("Config size is wrong! size:%d\n", size);
+		ret = -1;
+		goto exit;
+	}
+	data = malloc(size);
+	if (fdtdec_get_int_array(fdt_addr, node, config_name,
+				 data, size/sizeof(int))) {
+		printf("Failed to parse rdc config!\n");
+		ret = -1;
+		goto exit;
+	} else {
+		/* copy the rdc config */
+		memcpy(dst_addr, data, size);
+		ret = 0;
+	}
+
+exit:
+	if (data)
+		free(data);
+
+	/* Invalidate the buffer if no valid config found. */
+	if (ret < 0)
+		memset(dst_addr, 0, sizeof(uint32_t));
+
+	return ret;
+}
+#endif
+
+void board_spl_fit_post_load(const void *fit, struct spl_image_info *spl_image)
+{
+	if (IS_ENABLED(CONFIG_IMX_HAB) && !(spl_image->flags & SPL_FIT_BYPASS_POST_LOAD)) {
+		u32 offset = ALIGN(fdt_totalsize(fit), 0x1000);
+
+		if (imx_hab_authenticate_image((uintptr_t)fit,
+					       offset + IVT_SIZE + CSF_PAD_SIZE,
+					       offset)) {
+			panic("spl: ERROR:  image authentication unsuccessful\n");
+		}
+	}
+#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MN)
+#define MCU_RDC_MAGIC "mcu_rdc"
+	if (!(spl_image->flags & SPL_FIT_BYPASS_POST_LOAD)) {
+		memcpy((void *)CONFIG_IMX8M_MCU_RDC_START_CONFIG_ADDR, MCU_RDC_MAGIC, ALIGN(strlen(MCU_RDC_MAGIC), 4));
+		memcpy((void *)CONFIG_IMX8M_MCU_RDC_STOP_CONFIG_ADDR, MCU_RDC_MAGIC, ALIGN(strlen(MCU_RDC_MAGIC), 4));
+		board_handle_rdc_config(spl_image->fdt_addr, "start-config",
+					(void *)(CONFIG_IMX8M_MCU_RDC_START_CONFIG_ADDR + ALIGN(strlen(MCU_RDC_MAGIC), 4)));
+		board_handle_rdc_config(spl_image->fdt_addr, "stop-config",
+					(void *)(CONFIG_IMX8M_MCU_RDC_STOP_CONFIG_ADDR + ALIGN(strlen(MCU_RDC_MAGIC), 4)));
+	}
+#endif
+}
+
 #ifdef CONFIG_IMX_TRUSTY_OS
 int check_rpmb_blob(struct mmc *mmc);
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 4e638c7561..b40d604c05 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -35,7 +35,7 @@ struct spl_fit_info {
 	int conf_node;		/* FDT offset to selected configuration node */
 };
 
-__weak void board_spl_fit_post_load(const void *fit)
+__weak void board_spl_fit_post_load(const void *fit, struct spl_image_info *spl_image)
 {
 }
 
@@ -866,8 +866,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 
 	spl_image->flags |= SPL_FIT_FOUND;
 
-	if (IS_ENABLED(CONFIG_IMX_HAB) && !(spl_image->flags & SPL_FIT_BYPASS_POST_LOAD))
-		board_spl_fit_post_load(ctx.fit);
+	board_spl_fit_post_load(ctx.fit, spl_image);
 
 	return 0;
 }
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_boot.c b/drivers/fastboot/fb_fsl/fb_fsl_boot.c
index 24d8bc9a11..ca899014bb 100644
--- a/drivers/fastboot/fb_fsl/fb_fsl_boot.c
+++ b/drivers/fastboot/fb_fsl/fb_fsl_boot.c
@@ -191,8 +191,8 @@ static int do_bootmcu(struct cmd_tbl *cmdtp, int flag, int argc, char * const ar
 	char command[32];
 
 	ret = read_from_partition_multi(FASTBOOT_MCU_FIRMWARE_PARTITION,
-			0, ANDROID_MCU_FIRMWARE_SIZE, (void *)mcu_base_addr, &out_num_read);
-	if ((ret != 0) || (out_num_read != ANDROID_MCU_FIRMWARE_SIZE)) {
+			0, ANDROID_MCU_OS_PARTITION_SIZE, (void *)mcu_base_addr, &out_num_read);
+	if ((ret != 0) || (out_num_read != ANDROID_MCU_OS_PARTITION_SIZE)) {
 		printf("Read MCU images failed!\n");
 		return 1;
 	} else {
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c
index 59027c0755..4f930ac19c 100644
--- a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c
+++ b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c
@@ -217,7 +217,7 @@ static int _fastboot_parts_load_from_ptable(void)
 #ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
 	strcpy(ptable[PTN_MCU_OS_INDEX].name, FASTBOOT_MCU_FIRMWARE_PARTITION);
 	ptable[PTN_MCU_OS_INDEX].start = ANDROID_MCU_FIRMWARE_START / dev_desc->blksz;
-	ptable[PTN_MCU_OS_INDEX].length = ANDROID_MCU_FIRMWARE_SIZE / dev_desc->blksz;
+	ptable[PTN_MCU_OS_INDEX].length = ANDROID_MCU_OS_PARTITION_SIZE / dev_desc->blksz;
 	ptable[PTN_MCU_OS_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE;
 	ptable[PTN_MCU_OS_INDEX].partition_id = user_partition;
 	strcpy(ptable[PTN_MCU_OS_INDEX].fstype, "raw");
diff --git a/include/spl.h b/include/spl.h
index 89abf0d1ea..d44903fc0c 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -814,7 +814,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
  * board_spl_fit_post_load - allow process images after loading finished
  * @fit: Pointer to a valid Flattened Image Tree blob
  */
-void board_spl_fit_post_load(const void *fit);
+void board_spl_fit_post_load(const void *fit, struct spl_image_info *spl_image);
 
 /**
  * board_spl_fit_size_align - specific size align before processing payload