mpc83xx: Migrate CONFIG_LCRR_* to Kconfig

Migrate the CONFIG_LCRR_* settings to Kconfig.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

83 files changed, 281 insertions, 120 deletions

diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 59faa78d24..af8facad53 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -129,28 +129,6 @@ void cpu_init_f (volatile immap_t * im)
 		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 #endif
 		0;
-	__be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-		LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
-		LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-		LCRR_CLKDIV |
-#endif
-		0;
-	__be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-		CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
-		CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-		CONFIG_SYS_LCRR_CLKDIV |
-#endif
-		0;
 
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
index 82c2489178..a6b42a29af 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
@@ -1,5 +1,6 @@
 menu "Initial register configuration"
 
 source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
 
 endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
new file mode 100644
index 0000000000..e6b6130de2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
@@ -0,0 +1,139 @@
+menu "LCRR - Clock Ratio Register register"
+
+if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
+
+choice
+	prompt "DLL bypass"
+
+config LCRR_DBYP_UNSET
+	bool "Don't set value"
+
+config LCRR_DBYP_PLL_ENABLED
+	bool "PLL enabled"
+
+config LCRR_DBYP_PLL_BYPASSED
+	bool "PLL bypassed"
+
+endchoice
+
+endif
+
+if ARCH_MPC834X || ARCH_MPC8360
+
+choice
+	prompt "Additional delay cycles for SDRAM control signals"
+
+config LCRR_BUFCMDC_UNSET
+	bool "Don't set value"
+
+config LCRR_BUFCMDC_4
+	bool "4"
+
+config LCRR_BUFCMDC_1
+	bool "1"
+
+config LCRR_BUFCMDC_2
+	bool "2"
+
+config LCRR_BUFCMDC_3
+	bool "3"
+
+endchoice
+
+choice
+	prompt "Extended CAS latency"
+
+config LCRR_ECL_UNSET
+	bool "Don't set value"
+
+config LCRR_ECL_4
+	bool "4"
+
+config LCRR_ECL_5
+	bool "5"
+
+config LCRR_ECL_6
+	bool "6"
+
+config LCRR_ECL_7
+	bool "7"
+
+endchoice
+
+endif # ARCH_MPC834X || ARCH_MPC8360
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address delay cycles"
+
+config LCRR_EADC_UNSET
+	bool "Don't set value"
+
+config LCRR_EADC_4
+	bool "4"
+
+config LCRR_EADC_1
+	bool "1"
+
+config LCRR_EADC_2
+	bool "2"
+
+config LCRR_EADC_3
+	bool "3"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+choice
+	prompt "System clock divider"
+
+config LCRR_CLKDIV_UNSET
+	bool "Don't set value"
+
+config LCRR_CLKDIV_2
+	bool "2"
+
+config LCRR_CLKDIV_4
+	bool "4"
+
+config LCRR_CLKDIV_8
+	bool "8"
+
+endchoice
+
+config LCRR_DBYP
+	hex
+	default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
+	default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
+
+config LCRR_BUFCMDC
+	hex
+	default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
+	default 0x10000000 if LCRR_BUFCMDC_1
+	default 0x20000000 if LCRR_BUFCMDC_2
+	default 0x30000000 if LCRR_BUFCMDC_3
+
+config LCRR_ECL
+	hex
+	default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
+	default 0x1000000 if LCRR_ECL_5
+	default 0x2000000 if LCRR_ECL_6
+	default 0x3000000 if LCRR_ECL_7
+
+config LCRR_EADC
+	hex
+	default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
+	default 0x10000 if LCRR_EADC_1
+	default 0x20000 if LCRR_EADC_2
+	default 0x30000 if LCRR_EADC_3
+
+config LCRR_CLKDIV
+	hex
+	default 0x0 if LCRR_CLKDIV_UNSET
+	default 0x2 if LCRR_CLKDIV_2
+	default 0x4 if LCRR_CLKDIV_4
+	default 0x8 if LCRR_CLKDIV_8
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
index d61c70f1fa..63aa5c9466 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
+++ b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
@@ -41,3 +41,39 @@
 		CONFIG_SPCR_TSEC2EP |
 #endif
 		0;
+
+	const __be32 lcrr_mask =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+		LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+		LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+		LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+		LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+		LCRR_CLKDIV |
+#endif
+		0;
+
+	const __be32 lcrr_val =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+		CONFIG_LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+		CONFIG_LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+		CONFIG_LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+		CONFIG_LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+		CONFIG_LCRR_CLKDIV |
+#endif
+		0;
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index a01ff8920b..1a38ebd549 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -73,6 +73,8 @@ CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
 CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index b368aee966..04eb29ab9e 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -159,3 +159,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
 CONFIG_OR2_XACS_EXTENDED=y
 CONFIG_OR2_TRLX_RELAXED=y
 CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index ddf9060df4..8bbeb97778 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -158,3 +158,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
 CONFIG_OR2_XACS_EXTENDED=y
 CONFIG_OR2_TRLX_RELAXED=y
 CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 7c16364d3f..29b12d0040 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -167,3 +167,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
 CONFIG_OR2_XACS_EXTENDED=y
 CONFIG_OR2_TRLX_RELAXED=y
 CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index ab8e315e0d..2dc31edccb 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -166,3 +166,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
 CONFIG_OR2_XACS_EXTENDED=y
 CONFIG_OR2_TRLX_RELAXED=y
 CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index e5e1b7a29d..08b5cc5086 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -143,3 +143,5 @@ CONFIG_OR1_CHT_TWO_CLOCK=y
 CONFIG_OR1_CSCT_8_CYCLE=y
 CONFIG_OR1_CST_ONE_CLOCK=y
 CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index 08486f81a7..8ea942d7d9 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -108,3 +108,5 @@ CONFIG_OR0_XACS_EXTENDED=y
 CONFIG_OR0_XAM_SET=y
 CONFIG_OR0_TRLX_RELAXED=y
 CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index 807d3e391a..c39f449da9 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -143,3 +143,5 @@ CONFIG_OR3_XACS_EXTENDED=y
 CONFIG_OR3_XAM_SET=y
 CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index e328deb9fe..0e65d21bdb 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -163,3 +163,5 @@ CONFIG_OR3_XACS_EXTENDED=y
 CONFIG_OR3_XAM_SET=y
 CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index d5bf354eec..472384fa14 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -163,3 +163,5 @@ CONFIG_OR3_XACS_EXTENDED=y
 CONFIG_OR3_XAM_SET=y
 CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index 9d9d905118..ec8a94cd2a 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -160,3 +160,5 @@ CONFIG_OR3_XACS_EXTENDED=y
 CONFIG_OR3_XAM_SET=y
 CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 518f7114d7..8a26001f7f 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -142,3 +142,5 @@ CONFIG_OR3_XACS_EXTENDED=y
 CONFIG_OR3_XAM_SET=y
 CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig
index fa646f543f..35b394ba6a 100644
--- a/configs/MPC8349EMDS_PCI64_defconfig
+++ b/configs/MPC8349EMDS_PCI64_defconfig
@@ -104,3 +104,5 @@ CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_OR1_SCY_15=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig
index 8589470b2e..936458a441 100644
--- a/configs/MPC8349EMDS_SDRAM_defconfig
+++ b/configs/MPC8349EMDS_SDRAM_defconfig
@@ -113,3 +113,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_MPC8XXX_SPI=y
 CONFIG_OF_LIBFDT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig
index 8af1a3d3b2..9649967bf0 100644
--- a/configs/MPC8349EMDS_SLAVE_defconfig
+++ b/configs/MPC8349EMDS_SLAVE_defconfig
@@ -104,3 +104,5 @@ CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_OR1_SCY_15=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index b2b944a30d..bb0d166e4d 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -107,3 +107,5 @@ CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_OR1_SCY_15=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index fcd78338c9..eddb72b1e0 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -178,3 +178,5 @@ CONFIG_BR3_MACHINE_UPMA=y
 CONFIG_BR3_PORTSIZE_16BIT=y
 CONFIG_OR3_AM_32_KBYTES=y
 CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 319b8d8c40..b394da3a05 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -186,3 +186,5 @@ CONFIG_BR3_MACHINE_UPMA=y
 CONFIG_BR3_PORTSIZE_16BIT=y
 CONFIG_OR3_AM_32_KBYTES=y
 CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index f60527b361..274fbddf99 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -185,3 +185,5 @@ CONFIG_BR3_MACHINE_UPMA=y
 CONFIG_BR3_PORTSIZE_16BIT=y
 CONFIG_OR3_AM_32_KBYTES=y
 CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 33e536ce18..6e6fc54d51 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -178,3 +178,5 @@ CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_CHT_TWO_CLOCK=y
 CONFIG_OR3_CST_ONE_CLOCK=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig
index 7d1f405171..421e176226 100644
--- a/configs/MPC837XEMDS_SLAVE_defconfig
+++ b/configs/MPC837XEMDS_SLAVE_defconfig
@@ -131,3 +131,5 @@ CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_CHT_TWO_CLOCK=y
 CONFIG_OR3_CST_ONE_CLOCK=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index d4515cbb8c..cd03f3ff9e 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -154,3 +154,5 @@ CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_CHT_TWO_CLOCK=y
 CONFIG_OR3_CST_ONE_CLOCK=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
index 9730aefd54..c90ebc8d7e 100644
--- a/configs/MPC837XERDB_SLAVE_defconfig
+++ b/configs/MPC837XERDB_SLAVE_defconfig
@@ -132,3 +132,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
 CONFIG_OR2_XACS_EXTENDED=y
 CONFIG_OR2_TRLX_RELAXED=y
 CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 7bf081a20b..95f4796281 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -175,3 +175,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
 CONFIG_OR2_XACS_EXTENDED=y
 CONFIG_OR2_TRLX_RELAXED=y
 CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index f5746cfad7..9d9f105f75 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -147,3 +147,5 @@ CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
 CONFIG_OR0_CSNT_EARLIER=y
 CONFIG_OR0_SCY_5=y
 CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index 9c1ab75e00..bc4c2a91fb 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -131,3 +131,5 @@ CONFIG_OR1_XACS_EXTENDED=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_TRLX_RELAXED=y
 CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 0f1cc637cf..af93aef1be 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -129,3 +129,5 @@ CONFIG_OR1_XACS_EXTENDED=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_TRLX_RELAXED=y
 CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index f835868209..d9b1642671 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -170,3 +170,5 @@ CONFIG_OR3_AM_32_KBYTES=y
 CONFIG_OR3_CSNT_EARLIER=y
 CONFIG_OR3_SCY_1=y
 CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 7751e5a898..941efcdf9a 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -192,3 +192,6 @@ CONFIG_OR4_CSNT_EARLIER=y
 CONFIG_OR4_EAD_EXTRA=y
 CONFIG_OR4_SCY_2=y
 CONFIG_OR4_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_LCRR_EADC_2=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 2bb3158873..4929a6039b 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -154,3 +154,6 @@ CONFIG_OR3_CSNT_EARLIER=y
 CONFIG_OR3_EAD_EXTRA=y
 CONFIG_OR3_SCY_2=y
 CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_LCRR_EADC_2=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 5eb5c939eb..afe424b8df 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -179,3 +179,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y
 CONFIG_OR3_AM_256_MBYTES=y
 CONFIG_OR3_SCY_4=y
 CONFIG_OR3_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 0ad8801df9..1a78680bd0 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -157,3 +157,6 @@ CONFIG_OR2_EAD_EXTRA=y
 CONFIG_OR2_SCY_2=y
 CONFIG_OR2_TRLX_RELAXED=y
 CONFIG_OR2_EHTR_4_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index 8dfc4438ad..d874149fe3 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -157,3 +157,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y
 CONFIG_OR3_AM_256_MBYTES=y
 CONFIG_OR3_SCY_5=y
 CONFIG_OR3_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 1a84ff5e0b..32d098028a 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -179,3 +179,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y
 CONFIG_OR3_AM_256_MBYTES=y
 CONFIG_OR3_SCY_4=y
 CONFIG_OR3_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index a746f195e6..26d9a7cf7a 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -177,3 +177,6 @@ CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
 CONFIG_OR3_CSNT_EARLIER=y
 CONFIG_OR3_SCY_3=y
 CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index f1559bef54..0789ecd586 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -122,3 +122,5 @@ CONFIG_BR2_PORTSIZE_8BIT=y
 CONFIG_OR2_AM_32_KBYTES=y
 CONFIG_OR2_SCY_4=y
 CONFIG_OR2_EHTR_1_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index a213f038ee..a363070dd8 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -106,3 +106,5 @@ CONFIG_OR0_XACS_EXTENDED=y
 CONFIG_OR0_XAM_SET=y
 CONFIG_OR0_TRLX_RELAXED=y
 CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 321c3d4073..215f31df28 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -106,3 +106,5 @@ CONFIG_OR0_XACS_EXTENDED=y
 CONFIG_OR0_XAM_SET=y
 CONFIG_OR0_TRLX_RELAXED=y
 CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index 865a3ef74a..d492b861d5 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -84,3 +84,5 @@ CONFIG_OR0_XACS_EXTENDED=y
 CONFIG_OR0_XAM_SET=y
 CONFIG_OR0_TRLX_RELAXED=y
 CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index b11a26c2fc..9f05b5693f 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_OR1_SCY_5=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index 72cb274348..a1f9662518 100644
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_OR1_SCY_5=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index f36404deb4..2477ee5ca4 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_OR1_SCY_5=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index 0ade98545a..da16d5dbfa 100644
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y
 CONFIG_OR1_SCY_5=y
 CONFIG_OR1_XAM_SET=y
 CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index 28e386db24..c970cde05e 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -175,3 +175,6 @@ CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
 CONFIG_OR3_CSNT_EARLIER=y
 CONFIG_OR3_SCY_3=y
 CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index fb18a46ec6..550f524a3c 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -157,3 +157,6 @@ CONFIG_OR2_EAD_EXTRA=y
 CONFIG_OR2_SCY_2=y
 CONFIG_OR2_TRLX_RELAXED=y
 CONFIG_OR2_EHTR_4_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index a034f302b2..d5ec8e5bf2 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -182,3 +182,6 @@ CONFIG_OR3_CSNT_EARLIER=y
 CONFIG_OR3_SCY_2=y
 CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_EHTR_4_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 79f6430f91..0a9521b251 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -145,3 +145,5 @@ CONFIG_OR3_SCY_15=y
 CONFIG_OR3_XACS_EXTENDED=y
 CONFIG_OR3_TRLX_RELAXED=y
 CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_3=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 9ac88c0a4b..24bbba1aa7 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -118,3 +118,4 @@ CONFIG_BR1_MACHINE_GPCM=y
 CONFIG_BR1_PORTSIZE_32BIT=y
 CONFIG_OR1_AM_256_KBYTES=y
 CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index c4b604cc0d..e625f8709c 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -126,8 +126,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
 
 /*
diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index aaf92fe37a..08c5b56da7 100644
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -191,8 +191,6 @@
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
 				| (0xFF << LBCR_BMT_SHIFT) \
 				| 0xF)	/* 0x0004ff0f */
diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 608565a139..2a39ffa6c2 100644
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -164,8 +164,6 @@
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
 				| (0xFF << LBCR_BMT_SHIFT) \
 				| 0xF)	/* 0x0004ff0f */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 10742ae312..b49022b916 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -121,8 +121,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
 #define CONFIG_FSL_ELBC		1
 
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 2ef16e543d..497c60bcda 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -118,8 +118,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 195d62ce50..520f01f177 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -118,8 +118,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 
 /*
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index b64a911838..2043344524 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -161,8 +161,6 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /*
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 35210ccfd2..70fc29e8ad 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -158,8 +158,6 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /*
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index d8e86f21ea..6f040a3d6d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -258,8 +258,6 @@ boards, we say we have two, but don't display a message if we find only one. */
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 				/* LB sdram refresh timer, about 6us */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 5d46907331..5f0050a97d 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -139,8 +139,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 #define CONFIG_FSL_ELBC		1
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index b6756c3794..ef23d00408 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -163,8 +163,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
 #define CONFIG_FSL_ELBC		1
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index d713c695f7..8171f8531b 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -16,18 +16,6 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 
-/*
- * Local Bus LCRR
- *    LCRR:  DLL bypass, Clock divider is 8
- *
- *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
- *
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
-
 /* board pre init: do not call, nothing to do */
 
 /* detect the number of flash banks */
diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index b4516267f1..a0642aef11 100644
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -104,7 +104,6 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 9cb5df4a72..0919bb544d 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -115,8 +115,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
 
 /*
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index bd8f786a58..174c181ffa 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -39,8 +39,6 @@
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CONFIG_SYS_LCRR_EADC		LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		(0x00040000 |\
 					 (0xFF << LBCR_BMT_SHIFT) |\
 					 0xF)
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index 08185894b8..7034c7033f 100644
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -297,13 +297,6 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 
 /*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_EADC		LCRR_EADC_2
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_4
-
-/*
  * PAXE on the local bus CS3
  */
 #define CONFIG_SYS_PAXE_BASE		0xA0000000
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index e0c3065ac6..bbf3783ef9 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -277,13 +277,6 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 
 /*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_EADC		LCRR_EADC_2
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_4
-
-/*
  * PAXE on the local bus CS3
  */
 #define CONFIG_SYS_PAXE_BASE		0xA0000000
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
index c2f4188a22..77dc6a93b1 100644
--- a/include/configs/kmopti2.h
+++ b/include/configs/kmopti2.h
@@ -294,10 +294,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index b1ba474e78..561ae7a148 100644
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -294,10 +294,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
index d3f7c2c4d3..b4ebde8ba5 100644
--- a/include/configs/kmtegr1.h
+++ b/include/configs/kmtegr1.h
@@ -346,10 +346,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /* must be after the include because KMBEC_FPGA is otherwise undefined */
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
index 796040995d..80f6f4daa4 100644
--- a/include/configs/kmtepr2.h
+++ b/include/configs/kmtepr2.h
@@ -294,10 +294,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
index cfbf150b11..9e301a9728 100644
--- a/include/configs/kmvect1.h
+++ b/include/configs/kmvect1.h
@@ -338,10 +338,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #define CONFIG_SYS_APP1_BASE		0xA0000000
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index ce3a899480..aca4a655e0 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -130,8 +130,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
 
 /*
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 775bbe417a..6bad651133 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -131,8 +131,6 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index e4584db7d5..69e22fb141 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -115,8 +115,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
 
 /*
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index e3653ea924..ad3323fd0e 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -291,10 +291,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #define CONFIG_SYS_APP1_BASE		0xA0000000
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
index 81e11d2236..466f75a44e 100644
--- a/include/configs/tuge1.h
+++ b/include/configs/tuge1.h
@@ -294,10 +294,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index 28416af225..02e24f002a 100644
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -294,10 +294,6 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 76fe3be446..8b20bfd100 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -133,9 +133,6 @@
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_3
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
-
 #define CONFIG_SYS_LBC_LBCR	0x00040000
 
 #define CONFIG_SYS_LBC_MRTPR	0x20000000
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 1a3a55b707..d50a5263a7 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -104,7 +104,6 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 30b8b55132..c6c4689a2f 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3203,9 +3203,6 @@ CONFIG_SYS_LBC_SDRAM_BASE_PHYS
 CONFIG_SYS_LBC_SDRAM_SIZE
 CONFIG_SYS_LB_SDRAM
 CONFIG_SYS_LCD_BASE
-CONFIG_SYS_LCRR_CLKDIV
-CONFIG_SYS_LCRR_DBYP
-CONFIG_SYS_LCRR_EADC
 CONFIG_SYS_LDB_CLOCK
 CONFIG_SYS_LDSCRIPT
 CONFIG_SYS_LED_BASE