Merge tag 'lf-5.15.71-2.2.2' into toradex_imx_lf_v2022.04

This pulls in the following commits:
git log --oneline --no-merges  ^HEAD lf-5.15.71-2.2.2

14b6c8f3e3b MA-20886 imx8ulp: Boot from recovery mode when pressing key
62ad7799b6c LF-7602: Device tree fixup based on compatible string
b35420da607 crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()
918dbf78bbb MA-20872 Revert "MA-18775 system will hang about 3s when boot up kernel"
ed2c3cbd6ac MA-20814 add fastboot command to erase u-boot env
a6762e28bf0 LF-6627: nand drvier fixups in sdboot on ls1043ardb-pd
d23cfa09767 LFU-426: qspihdr: Coverity Issue: unchecked return value
413b08f841f MLK-25850: imx8dxl_ddr3l_evk: change the default fdt file name
e91a047f54f LF-7382: fastboot: improve emmc write speed
205680f9f4b LFU-428 imx8ulp: Add warning for CAAM non-secure state failure
f405551dcc1 LF-7369-2 clk: imx93: update LPCG control API
676831be672 LF-7369-1 clk: imx: implement a clock gate driver for i.MX93
94c5bb2eb83 MA-20507-7 trusty: fix dereference null return value
6933487b4df LFU-427 imx93: Print ELE FW version
15b1ebb00cc LFU-393 imx93: Add reset cause print
f3b75e3317d LF-7332 imx8/ahab: sha256: enable image verification using ARMv8 crypto extention
330e2634143 LFU-423: usb: cdns3: gadget: Avoid using usb_ss after null check
58ba744cbad MLK-26034 imx6: Disable LCDIF clock before jumping to kernel
ae396d343a3 LF-6627: nand drvier fixups in nandboot on ls1043ardb-pd
0a99627b60e LFU-422-2 imx8ulp_evk: Enable the GD25LX256E support
c6c06de038f LFU-422-1 mtd: spi-nor: Add GigaDevice GD25LX256E NOR flash
032fab5e127 LFU-421 imx93_evk: Add imx93 low drive mode support on 11x11 EVK
d9f477625d3 LF-7332 armv8: SHA-256 using ARMv8 Crypto Extensions
53689e4f7db MA-20667 set metadata partition of type f2fs
f824cd01955 LFU-415 net: fec_mxc: Skip recv packet process when fec is halted
4e7c44e1f33 LFU-419 arm: dts: imx8mp: fix flexspi nand reg
957bdd9c925 LFU-418 imx8ulp: upower_hal: make code cleaner
361b23b98ed Revert "MLK-25478-1 efi: add Platform-Reset-Attack variables"
e1ed0611b5e Revert "MLK-25478-2 efi: clean memory and reset MemoryOverwriteRequestControl"
4998fef38a5 Revert "MLK-25478-3 workaround: disable verify time of signer and signee."
320096439b6 MA-20738 imx8ulp: bumps CONFIG_LMB_MAX_REGIONS
c244bdfd76c LFU-417-2 imx93_evk/qsb: Enable DDR inline ECC feature
026521c7d65 LFU-417-1 ddr: imx: imx9: Add DDR inline ECC support
a555a21be69 LFU-413 imx8ulp_evk: Remove CONFIG_BOOTDELAY=0 from ND defconfig
aaead5a2b8d LFU-416 imx: cmd_dek: Fix build warning in blob_encap_dek
933a3b25fe3 LF-7234 enable CONFIG_CMD_CRC32 and CONFIG_CRC32_VERIFY
97fc905e7f7 LFU-409: imx8dxl: fix the i.MX8DXL ddr3l NAND DQS iomux setting
aa4ebb66199 LFU-414 imx8ulp: clock: Update clocks to meet max rate restrictions
63d0579f397 LFU-410 imx: ele_ahab: Add ahab_sec_fuse_prog command
266dddae454 LFU-412 configs: imx93_evk: shrink mem= for jailhouse
5703d3ae37e LFU-411 imx8ulp: Always enable MIPI_DSI power switch
32965eb52f7 LFU-392 imx8ulp: upower: replace magic number with macro
beb5e5e3303 MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default
bb45dd592db LFU-408 imx93evk: config the pmic standby voltage for buck1
25e38cb4762 LFU-407-02 ddr: imx9: Change the saved ddr data base to 0x2051c000
a8fef10ab92 LFU-407-01 configs: imx93: Update spl stack & bss base address
8731024fe7e LFU-406 mx6ul/mx6ulz: Fix build break caused by RNG patch
a95afe08769 LF-7238 imx9: soc: Remove OPTEE memory from DRAM bank and MMU
19c3fdebf8d LFU-403-4 imx93_evk/qsb: Enable TMU sensor driver
e1703ec06a4 LFU-403-3 iMX93: soc: print current CPU temperature
050a94e6365 LFU-403-2 DTS: imx93: Update TMU node to sync with kernel
91e711a565c LFU-403-1 thermal: imx_tmu: Update TMU driver to support iMX93
78749666dd3 LFU-402-3 imx93_evk/qsb: Use API to set max ARM clock
401b9824f92 LFU-402-2 iMX93: clock: Add API to set max ARM core clock
e4722baa5af LFU-402-1 iMX93: soc: Get market segment and speed grading
432a4af9608 LFU-400 imx8ulp: clock: Clear dividers in PLL3DIV_PFD registers
53f06207782 LFU-399 imx8ulp: Reconfigure MRC3 for SRAM0 access
48a2221acc9 LFU-395 imx93: Add fused parts support
d8760a74793 LFU-398-7 imx93_9x9_qsb: Enable Flexspi NOR support
1f500a59670 LFU-398-6 imx93_qsb: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
ba4f72198f5 LFU-398-5 DTS: imx93-9x9-qsb: Add flexspi NOR nodes and pinctrl
d9f563336f7 LFU-398-4 imx93_11x11_evk: Enable Flexspi NOR support
c56f2132d53 LFU-398-3 imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
b6cbe6b1416 LFU-398-2 DTS: imx93-11x11-evk: Enable and update flexspi NOR
c45c4fb791b LFU-398-1 DTS: imx93: Update flexspi node in DTSi
fab973fe1df LFU-397 imx8m: clock: not configure reserved SRC register
4881ba99fa4 LFU-396-7 imx93_9x9_qsp_defconfig: support splash screen
60e0e629f99 LFU-396-6 arm: dts: add imx93 9x9 ontat panel dts
fffc330cf1a LFU-396-5 imx9: clock: add 300MHz fracn pll table
ef6a3d9cc38 LFU-396-4 video: nxp: imx: add Add i.MX93 parallel display format encoder driver
5f414738a5f LFU-396-3 video: nxp: imx_lcdifv3: support VSYNC/HSYNC active low
21eb66fe1f8 LFU-396-2 video: nxp: imx: dsi: force DISPLAY_FLAGS_HSYNC_HIGH & DISPLAY_FLAGS_VSYNC_HIGH
88132ed0b4e LFU-396-1 video: simple_panel: make backlight optional
65287dc074d LF-7055: video: imx: Add set_parent calls to LVDS initialization
167f65006fb MLK-26021 imx93: add 9x9 qsb lpddr4 board
0a6297a290e MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default
8789f3ca3e4 PLATSEC-1781-2 MX6: Device tree fix-up
60555c4a445 PLATSEC-1781-1 mx6ull:Add config CONFIG_OF_SYSTEM_SETUP
48b1d6e34fd MA-20149 set fs type of android partitions
9710cc4840e LFOPTEE-177 imx93evk: enable cmd_dek command
f0721d67f03 LFOPTEE-177 imx8ulp: enable cmd_dek command
bf07f5166bf LFOPTEE-177 imx: cmd_dek: add ELE DEK Blob generation support
6de56c3f629 LFOPTEE-177 s400_api: add DEK Blob generation

Conflicts:
	drivers/crypto/fsl/fsl_hash.c
	commit 41b2182af73 ("crypto: fsl_hash: Remove unnecessary
	alignment check in caam_hash()")
	Both NXP and TXD branch did cherry-picking that commit, but NXP
	additionally removed a debug print (not present in master)
	while the TDX branch did not. Resolved by doing it the NXP way.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

1 files changed, 157 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv8/crypto/sha2-ce-core.S b/arch/arm/cpu/armv8/crypto/sha2-ce-core.S
new file mode 100644
index 00000000000..ad76362dff8
--- /dev/null
+++ b/arch/arm/cpu/armv8/crypto/sha2-ce-core.S
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
+ *
+ * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
+ * Copyright 2022 NXP
+ */
+
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+	.text
+	.arch		armv8-a+crypto
+
+	dga		.req	q20
+	dgav		.req	v20
+	dgb		.req	q21
+	dgbv		.req	v21
+
+	t0		.req	v22
+	t1		.req	v23
+
+	dg0q		.req	q24
+	dg0v		.req	v24
+	dg1q		.req	q25
+	dg1v		.req	v25
+	dg2q		.req	q26
+	dg2v		.req	v26
+
+	.macro		add_only, ev, rc, s0
+	mov		dg2v.16b, dg0v.16b
+	.ifeq		\ev
+	add		t1.4s, v\s0\().4s, \rc\().4s
+	sha256h		dg0q, dg1q, t0.4s
+	sha256h2	dg1q, dg2q, t0.4s
+	.else
+	.ifnb		\s0
+	add		t0.4s, v\s0\().4s, \rc\().4s
+	.endif
+	sha256h		dg0q, dg1q, t1.4s
+	sha256h2	dg1q, dg2q, t1.4s
+	.endif
+	.endm
+
+	.macro		add_update, ev, rc, s0, s1, s2, s3
+	sha256su0	v\s0\().4s, v\s1\().4s
+	add_only	\ev, \rc, \s1
+	sha256su1	v\s0\().4s, v\s2\().4s, v\s3\().4s
+	.endm
+
+	/*
+	 * The SHA-256 round constants
+	 */
+	.section	".rodata", "a"
+	.align		4
+.Lsha2_rcon:
+	.word		0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
+	.word		0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
+	.word		0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
+	.word		0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
+	.word		0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
+	.word		0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
+	.word		0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
+	.word		0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
+	.word		0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
+	.word		0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
+	.word		0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
+	.word		0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
+	.word		0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
+	.word		0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
+	.word		0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
+	.word		0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+
+	/*
+	 * void sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src,
+	 *			  int blocks)
+	 */
+	.text
+ENTRY(sha2_ce_transform)
+	/* load round constants */
+	adr_l		x8, .Lsha2_rcon
+	ld1		{ v0.4s- v3.4s}, [x8], #64
+	ld1		{ v4.4s- v7.4s}, [x8], #64
+	ld1		{ v8.4s-v11.4s}, [x8], #64
+	ld1		{v12.4s-v15.4s}, [x8]
+
+	/* load state */
+	ld1		{dgav.4s, dgbv.4s}, [x0]
+
+	/* load sha256_ce_state::finalize */
+	ldr_l		w4, sha256_ce_offsetof_finalize, x4
+	ldr		w4, [x0, x4]
+
+	/* load input */
+0:	ld1		{v16.4s-v19.4s}, [x1], #64
+	sub		w2, w2, #1
+
+CPU_LE(	rev32		v16.16b, v16.16b	)
+CPU_LE(	rev32		v17.16b, v17.16b	)
+CPU_LE(	rev32		v18.16b, v18.16b	)
+CPU_LE(	rev32		v19.16b, v19.16b	)
+
+1:	add		t0.4s, v16.4s, v0.4s
+	mov		dg0v.16b, dgav.16b
+	mov		dg1v.16b, dgbv.16b
+
+	add_update	0,  v1, 16, 17, 18, 19
+	add_update	1,  v2, 17, 18, 19, 16
+	add_update	0,  v3, 18, 19, 16, 17
+	add_update	1,  v4, 19, 16, 17, 18
+
+	add_update	0,  v5, 16, 17, 18, 19
+	add_update	1,  v6, 17, 18, 19, 16
+	add_update	0,  v7, 18, 19, 16, 17
+	add_update	1,  v8, 19, 16, 17, 18
+
+	add_update	0,  v9, 16, 17, 18, 19
+	add_update	1, v10, 17, 18, 19, 16
+	add_update	0, v11, 18, 19, 16, 17
+	add_update	1, v12, 19, 16, 17, 18
+
+	add_only	0, v13, 17
+	add_only	1, v14, 18
+	add_only	0, v15, 19
+	add_only	1
+
+	/* update state */
+	add		dgav.4s, dgav.4s, dg0v.4s
+	add		dgbv.4s, dgbv.4s, dg1v.4s
+
+	/* handled all input blocks? */
+	cbz		w2, 2f
+	b		0b
+
+	/*
+	 * Final block: add padding and total bit count.
+	 * Skip if the input size was not a round multiple of the block size,
+	 * the padding is handled by the C code in that case.
+	 */
+2:	cbz		x4, 3f
+	ldr_l		w4, sha256_ce_offsetof_count, x4
+	ldr		x4, [x0, x4]
+	movi		v17.2d, #0
+	mov		x8, #0x80000000
+	movi		v18.2d, #0
+	ror		x7, x4, #29		// ror(lsl(x4, 3), 32)
+	fmov		d16, x8
+	mov		x4, #0
+	mov		v19.d[0], xzr
+	mov		v19.d[1], x7
+	b		1b
+
+	/* store new state */
+3:	st1		{dgav.4s, dgbv.4s}, [x0]
+	mov		w0, w2
+	ret
+ENDPROC(sha2_ce_transform)