diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-10-05 15:27:06 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-10-07 12:26:15 +0200 |
| commit | e60f74907d65fb79f41c0f797407cb21da922c47 (patch) | |
| tree | de7bdbb7ef2c1b83076fb966b7998cfa1c917266 /arch/arm/dts/imx7-colibri.dts | |
| parent | bdad02e1e2aa2c4efc3fe8752c1340cc558e39dc (diff) | |
arm: dts: imx7: add basic i.MX 7/Colibri iMX7 device tree
Add base device for NXP i.MX 7Solo/7Dual. The two SoC are very
similar and hence can share the same device tree for boot loaders
purpose.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/dts/imx7-colibri.dts')
| -rw-r--r-- | arch/arm/dts/imx7-colibri.dts | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts new file mode 100644 index 0000000000..f2da09684f --- /dev/null +++ b/arch/arm/dts/imx7-colibri.dts @@ -0,0 +1,92 @@ +/* + * Copyright 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "imx7.dtsi" + +/ { + model = "Toradex Colibri iMX7S/D"; + compatible = "toradex,imx7-colibri", "fsl,imx7"; + + chosen { + stdout-path = &uart1; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpio-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 + >; + }; + + pinctrl_uart1_ctrl1: uart1-ctrl1-grp { + fsl,pins = < + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f + >; + }; +}; |