diff options
| author | Ye Li <ye.li@nxp.com> | 2018-05-30 00:14:12 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-05-31 06:17:27 -0700 |
| commit | 31c500c42103957de36698376174254adcacf794 (patch) | |
| tree | 98486bc92269b5e69f71fb7f3274d2d9dbe3f02d /arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts | |
| parent | d7569c2e4531454564849a39b59f18f373b02411 (diff) | |
MLK-18460-1 DTS: mx7d_12x12_arm2: Add board DTS files for DDR3/LPDDR3 ARM2
Add DTS files to support iMX7D 12x12 LPDDR3 and DDR3 ARM2 boards.
Due to pin conflicts, need specified DTS for SPINOR, QSPI on LPDDR3
ARM2.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts')
| -rw-r--r-- | arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts new file mode 100644 index 0000000000..c26556d059 --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_qspi1_1>; + pinctrl-1 = <&pinctrl_qspi1_1>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; |