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| author | Ye Li <ye.li@nxp.com> | 2022-09-20 16:19:09 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2022-10-08 21:33:43 +0800 |
| commit | 16e8414193985cf7a171f7b79e12ff30700157ba (patch) | |
| tree | 524aaf502b895cdf88bbfe5d8e8acb98ab81eba1 /arch/arm/dts/imx8mm-ab2-u-boot.dtsi | |
| parent | 50758c92e8fd1544a2d47da0b483a741863b7981 (diff) | |
LFU-400 imx8ulp: clock: Clear dividers in PLL3DIV_PFD registers
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But when MROM-3029 is applied, ROM will set
PLL3 pfd1div2 to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 91eb5a47b996b531c5fda5e421d35f54f486c548)
Diffstat (limited to 'arch/arm/dts/imx8mm-ab2-u-boot.dtsi')
0 files changed, 0 insertions, 0 deletions