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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2023-04-05 08:21:17 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2023-04-05 08:21:17 +0200 |
| commit | 5ecbc52530b00a6e2f39658be54d959c27a4f93d (patch) | |
| tree | 6de0c4375e2a7da8914436a192d0ed19c4eaa1ef /arch/arm/dts/k3-am62a7-sk.dts | |
| parent | 1599df538a93a3848f82b21b4ac6f1f96abd676e (diff) | |
arm: dts: k3-am625-verdin-lpddr4-1600MTs: update to sysconfig v0.09.08
Update LPDDR4 RAM timings to what the online AM62x SysConfig DDR
Subsystem Register Configuration Tool v0.09.08 generates which supports
bit swizzle configuration. From its README:
v9.08
-added automatic change of RL, WL and nWR when frequency is changed
-added DQ swizzle and byte swap configuration flexibilty for AM62x/AM62A LPDDR4
-PHY_CAL_CLK updated divider values for higher frequencies
-CS ODT fix bug introduced in previous release
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm/dts/k3-am62a7-sk.dts')
0 files changed, 0 insertions, 0 deletions