diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-22 07:42:23 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-23 01:00:39 +0900 |
| commit | 35343a2648ab42b178e94524404af9b3f4133343 (patch) | |
| tree | dab81e90932a813bb201bf142540eb5c32f4760d /arch/arm/dts/uniphier-common32.dtsi | |
| parent | 6dc5b6b1ff030a811d1747c19009d9f3b0908099 (diff) | |
ARM: dts: uniphier: sync clock/reset controller nodes with Linux
Sync device trees with Linux for easier DT life.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/dts/uniphier-common32.dtsi')
| -rw-r--r-- | arch/arm/dts/uniphier-common32.dtsi | 56 |
1 files changed, 40 insertions, 16 deletions
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index b0b2b57bb9..e4410339eb 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -31,7 +31,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; }; serial1: serial@54006900 { @@ -41,7 +41,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; }; serial2: serial@54006a00 { @@ -51,7 +51,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; }; serial3: serial@54006b00 { @@ -61,7 +61,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; }; system_bus: system-bus@58c00000 { @@ -79,16 +79,33 @@ reg = <0x59801000 0x400>; }; - mio: mioctrl@59810000 { - /* specify compatible in each SoC DTSI */ + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - #clock-cells = <1>; + u-boot,dm-pre-reloc; + + mio_clk: clock { + #clock-cells = <1>; + }; + + mio_rst: reset { + #reset-cells = <1>; + }; }; - peri: perictrl@59820000 { - /* specify compatible in each SoC DTSI */ + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; reg = <0x59820000 0x200>; - #clock-cells = <1>; + + peri_clk: clock { + #clock-cells = <1>; + }; + + peri_rst: reset { + #reset-cells = <1>; + }; }; timer@60000200 { @@ -114,7 +131,8 @@ }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; u-boot,dm-pre-reloc; @@ -124,12 +142,18 @@ }; }; - sysctrl: sysctrl@61840000 { - /* specify compatible in each SoC DTSI */ + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; reg = <0x61840000 0x4000>; - #clock-cells = <1>; - clock-names = "ref"; - clocks = <&refclk>; + + sys_clk: clock { + #clock-cells = <1>; + }; + + sys_rst: reset { + #reset-cells = <1>; + }; }; nand: nand@68000000 { |