diff options
author | Stefan Agner <stefan.agner@toradex.com> | 2018-05-29 18:54:08 +0200 |
---|---|---|
committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-06-06 13:17:12 +0200 |
commit | 2881fc12d952a7907ae58aff5cecf791055f2301 (patch) | |
tree | e48c83ffb9d6c95620dd504d8c5f6e97a75faa6e /arch/arm/imx-common/ddrmc-vf610.c | |
parent | 3ad050d4e42d2c5125c196ddd8bf213f0c387b07 (diff) |
ARM: vf610: fix initialization completion detection
The CR80 register has multiple interrupt bits, the code is supposed
to check bit 8 but instead uses a logical and. In most cases this
probably did not affect real operations since at that stage typically
none of the other bits are set.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm/imx-common/ddrmc-vf610.c')
-rw-r--r-- | arch/arm/imx-common/ddrmc-vf610.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c index 9bc56f6ac1..8582ad8c2a 100644 --- a/arch/arm/imx-common/ddrmc-vf610.c +++ b/arch/arm/imx-common/ddrmc-vf610.c @@ -232,6 +232,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, /* all inits done, start the DDR controller */ writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); - while (!(readl(&ddrmr->cr[80]) && 0x100)) + while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE)) udelay(10); + writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]); } |