diff options
| author | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-08-13 14:27:01 +0200 |
|---|---|---|
| committer | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-08-16 09:34:07 +0200 |
| commit | c461e51d55bfc253aafed227c9c05dd7d2e9403d (patch) | |
| tree | 15c2fecce96a3ab7ff24eb0f2e4e60c4b9ca1fd6 /arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h | |
| parent | d2f2357ae225c35e94092e4d3d53dcabbbe12325 (diff) | |
MLK-18502: board:imx8mm_evk enable tzasc
Enable TZASC on i.MX 8mm.
There is a need on 8MM to enable
the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit d72b8baecd8495cfba990b999fe390937859ad75)
Diffstat (limited to 'arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h index b46e1ababa..c1f3a8e64f 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h @@ -125,6 +125,7 @@ #define IOMUXC_GPR22 (IOMUXC_GPR_BASE_ADDR + 0x58) #define GPR_TZASC_EN (1 << 0) +#define GPR_TZASC_SWAP_ID (1 << 1) #define GPR_TZASC_EN_LOCK (1 << 16) #define CNTCR_OFF 0x00 |