MLK-21830-1 imx8qm: Update soc codes for iMX8QM

Add CPU type, Kconfig for iMX8QM and update SoC codes.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 3512fc146095df33882ae45a62174924b7aac58c)
(cherry picked from commit 1d5b77f78c09e572975e722b3ed908e6becdf337)
(cherry picked from commit f73c232781239c5f54148b5da2061a173eb6a583)
(cherry picked from commit 8e1aa344a731d47fc12dc5be3105b0fa0ceecf5a)

2 files changed, 132 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-imx8/i2c.h b/arch/arm/include/asm/arch-imx8/i2c.h
new file mode 100644
index 0000000000..ea2b83ee7e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/i2c.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+#ifndef __ASM_ARCH_IMX8_I2C_H__
+#define __ASM_ARCH_IMX8_I2C_H__
+
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/lpcg.h>
+
+struct imx_i2c_map {
+	unsigned index;
+	sc_rsrc_t rsrc;
+	u32 lpcg[4];
+};
+
+static struct imx_i2c_map imx_i2c_desc[] = {
+	{0, SC_R_I2C_0, {LPI2C_0_LPCG}},
+	{1, SC_R_I2C_1, {LPI2C_1_LPCG}},
+	{2, SC_R_I2C_2, {LPI2C_2_LPCG}},
+	{3, SC_R_I2C_3, {LPI2C_3_LPCG}},
+#ifdef CONFIG_IMX8QM
+	{4, SC_R_I2C_4, {LPI2C_4_LPCG}},
+	{5, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c0 */
+	{6, SC_R_LVDS_0_I2C_1, {DI_LVDS_0_LPCG + 0x14}}, /* lvds0 i2c1 */
+	{7, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c0 */
+	{8, SC_R_LVDS_1_I2C_1, {DI_LVDS_1_LPCG + 0x14}}, /* lvds1 i2c1 */
+#endif
+	{9, SC_R_CSI_0_I2C_0, {MIPI_CSI_0_LPCG + 0x14}},
+#ifdef CONFIG_IMX8QM
+	{10, SC_R_CSI_1_I2C_0, {MIPI_CSI_1_LPCG + 0x14}},
+	{11, SC_R_HDMI_I2C_0, {DI_HDMI_LPCG}},
+	{12, SC_R_HDMI_RX_I2C_0, {RX_HDMI_LPCG + 0x10, RX_HDMI_LPCG + 0x14, RX_HDMI_LPCG + 0x18, RX_HDMI_LPCG + 0x1C}},
+	{13, SC_R_MIPI_0_I2C_0, {MIPI_DSI_0_LPCG + 0x14, MIPI_DSI_0_LPCG + 0x18, MIPI_DSI_0_LPCG + 0x1c}},
+	{14, SC_R_MIPI_0_I2C_1, {MIPI_DSI_0_LPCG + 0x24, MIPI_DSI_0_LPCG + 0x28, MIPI_DSI_0_LPCG + 0x2c}},
+	{15, SC_R_MIPI_1_I2C_0, {MIPI_DSI_1_LPCG + 0x14, MIPI_DSI_1_LPCG + 0x18, MIPI_DSI_1_LPCG + 0x1c}},
+	{16, SC_R_MIPI_1_I2C_1, {MIPI_DSI_1_LPCG + 0x24, MIPI_DSI_1_LPCG + 0x28, MIPI_DSI_1_LPCG + 0x2c}},
+#else
+	{13, SC_R_MIPI_0_I2C_0, {DI_MIPI0_LPCG + 0x10}},
+	{14, SC_R_MIPI_0_I2C_1, {DI_MIPI0_LPCG + 0x14}},
+	{15, SC_R_MIPI_1_I2C_0, {DI_MIPI1_LPCG + 0x10}},
+	{16, SC_R_MIPI_1_I2C_1, {DI_MIPI1_LPCG + 0x14}},
+#endif
+};
+#endif /* __ASM_ARCH_IMX8_I2C_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index 2d64b0604b..c543e7d1ba 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -35,6 +35,13 @@
 #define MIPI1_SS_BASE		0x56240000
 #endif
 
+#ifdef CONFIG_IMX8QM
+#define LVDS0_PHYCTRL_BASE 0x56241000
+#define LVDS1_PHYCTRL_BASE 0x57241000
+#define MIPI0_SS_BASE 0x56220000
+#define MIPI1_SS_BASE 0x57220000
+#endif
+
 #define APBH_DMA_ARB_BASE_ADDR	0x5B810000
 #define APBH_DMA_ARB_END_ADDR	0x5B81FFFF
 #define MXS_APBH_BASE		APBH_DMA_ARB_BASE_ADDR
@@ -50,4 +57,82 @@
 #define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
 
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#include <stdbool.h>
+
+bool is_usb_boot(void);
+void disconnect_from_pc(void);
+#define is_boot_from_usb  is_usb_boot
+
+struct usbphy_regs {
+	u32	usbphy_pwd;			/* 0x000 */
+	u32	usbphy_pwd_set;			/* 0x004 */
+	u32	usbphy_pwd_clr;			/* 0x008 */
+	u32	usbphy_pwd_tog;			/* 0x00c */
+	u32	usbphy_tx;			/* 0x010 */
+	u32	usbphy_tx_set;			/* 0x014 */
+	u32	usbphy_tx_clr;			/* 0x018 */
+	u32	usbphy_tx_tog;			/* 0x01c */
+	u32	usbphy_rx;			/* 0x020 */
+	u32	usbphy_rx_set;			/* 0x024 */
+	u32	usbphy_rx_clr;			/* 0x028 */
+	u32	usbphy_rx_tog;			/* 0x02c */
+	u32	usbphy_ctrl;			/* 0x030 */
+	u32	usbphy_ctrl_set;		/* 0x034 */
+	u32	usbphy_ctrl_clr;		/* 0x038 */
+	u32	usbphy_ctrl_tog;		/* 0x03c */
+	u32	usbphy_status;			/* 0x040 */
+	u32	reserved0[3];
+	u32	usbphy_debug0;			/* 0x050 */
+	u32	usbphy_debug0_set;		/* 0x054 */
+	u32	usbphy_debug0_clr;		/* 0x058 */
+	u32	usbphy_debug0_tog;		/* 0x05c */
+	u32	reserved1[4];
+	u32	usbphy_debug1;			/* 0x070 */
+	u32	usbphy_debug1_set;		/* 0x074 */
+	u32	usbphy_debug1_clr;		/* 0x078 */
+	u32	usbphy_debug1_tog;		/* 0x07c */
+	u32	usbphy_version;			/* 0x080 */
+	u32	reserved2[7];
+	u32	usb1_pll_480_ctrl;		/* 0x0a0 */
+	u32	usb1_pll_480_ctrl_set;		/* 0x0a4 */
+	u32	usb1_pll_480_ctrl_clr;		/* 0x0a8 */
+	u32	usb1_pll_480_ctrl_tog;		/* 0x0ac */
+	u32	reserved3[4];
+	u32	usb1_vbus_detect;		/* 0xc0 */
+	u32	usb1_vbus_detect_set;		/* 0xc4 */
+	u32	usb1_vbus_detect_clr;		/* 0xc8 */
+	u32	usb1_vbus_detect_tog;		/* 0xcc */
+	u32	usb1_vbus_det_stat;		/* 0xd0 */
+	u32	reserved4[3];
+	u32	usb1_chrg_detect;		/* 0xe0 */
+	u32	usb1_chrg_detect_set;		/* 0xe4 */
+	u32	usb1_chrg_detect_clr;		/* 0xe8 */
+	u32	usb1_chrg_detect_tog;		/* 0xec */
+	u32	usb1_chrg_det_stat;		/* 0xf0 */
+	u32	reserved5[3];
+	u32	usbphy_anactrl;			/* 0x100 */
+	u32	usbphy_anactrl_set;		/* 0x104 */
+	u32	usbphy_anactrl_clr;		/* 0x108 */
+	u32	usbphy_anactrl_tog;		/* 0x10c */
+	u32	usb1_loopback;			/* 0x110 */
+	u32	usb1_loopback_set;		/* 0x114 */
+	u32	usb1_loopback_clr;		/* 0x118 */
+	u32	usb1_loopback_tog;		/* 0x11c */
+	u32	usb1_loopback_hsfscnt;		/* 0x120 */
+	u32	usb1_loopback_hsfscnt_set;	/* 0x124 */
+	u32	usb1_loopback_hsfscnt_clr;	/* 0x128 */
+	u32	usb1_loopback_hsfscnt_tog;	/* 0x12c */
+	u32	usphy_trim_override_en;		/* 0x130 */
+	u32	usphy_trim_override_en_set;	/* 0x134 */
+	u32	usphy_trim_override_en_clr;	/* 0x138 */
+	u32	usphy_trim_override_en_tog;	/* 0x13c */
+	u32	usb1_pfda_ctrl1;		/* 0x140 */
+	u32	usb1_pfda_ctrl1_set;		/* 0x144 */
+	u32	usb1_pfda_ctrl1_clr;		/* 0x148 */
+	u32	usb1_pfda_ctrl1_tog;		/* 0x14c */
+};
+#endif
+
 #endif /* __ASM_ARCH_IMX8_REGS_H__ */