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authorNicolas Ferre <nicolas.ferre@microchip.com>2020-10-07 16:53:44 +0200
committerEugen Hristev <eugen.hristev@microchip.com>2020-10-19 09:19:53 +0300
commitdb228c5b467f53b639e28a9b92ce30a8695e0f8d (patch)
tree1333fd9173336a2fc76d4c221877a5292fd60893 /arch/arm/mach-at91
parent42f2dfa7891127e46928526bcaddb906f4a9d52e (diff)
ARM: at91: Add chip ID for SAM9X60 SiP
SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/arm926ejs/sam9x60_devices.c6
-rw-r--r--arch/arm/mach-at91/include/mach/sam9x60.h3
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
index d463bbc788..e3d3dd880c 100644
--- a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
@@ -44,6 +44,12 @@ char *get_cpu_name(void)
switch (extension_id) {
case ARCH_EXID_SAM9X60:
return "SAM9X60";
+ case ARCH_EXID_SAM9X60_D6K:
+ return "SAM9X60 8MiB SDRAM SiP";
+ case ARCH_EXID_SAM9X60_D5M:
+ return "SAM9X60 64MiB DDR2 SiP";
+ case ARCH_EXID_SAM9X60_D1G:
+ return "SAM9X60 128MiB DDR2 SiP";
default:
return "Unknown CPU type";
}
diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h
index 0f00a9ae87..b7f43226b7 100644
--- a/arch/arm/mach-at91/include/mach/sam9x60.h
+++ b/arch/arm/mach-at91/include/mach/sam9x60.h
@@ -128,6 +128,9 @@
#define ARCH_ID_SAM9X60 0x819b35a0
#define ARCH_ID_VERSION_MASK 0x1f
#define ARCH_EXID_SAM9X60 0x00000000
+#define ARCH_EXID_SAM9X60_D6K 0x00000011
+#define ARCH_EXID_SAM9X60_D5M 0x00000001
+#define ARCH_EXID_SAM9X60_D1G 0x00000010
#define cpu_is_sam9x60() (get_chip_id() == ARCH_ID_SAM9X60)