diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2017-05-03 16:58:26 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-08 12:34:29 -0400 |
| commit | ee3c6532be343e495d11adfe15a457d24d9747d9 (patch) | |
| tree | 202b389517d50e835d6ce1e1a79d7ec2db979e67 /arch/arm/mach-keystone | |
| parent | c5f177debc8b430c0a0038a9d8f6309eb3bd6299 (diff) | |
ARM: keystone2: Add support for getting external clock dynamically
One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-keystone')
| -rw-r--r-- | arch/arm/mach-keystone/clock.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-keystone/include/mach/clock.h | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 68f898036f..645bd9629e 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -284,7 +284,7 @@ static unsigned long pll_freq_get(int pll) u32 tmp, reg; if (pll == MAIN_PLL) { - ret = external_clk[sys_clk]; + ret = get_external_clk(sys_clk); if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) { /* PLL mode */ tmp = __raw_readl(KS2_MAINPLLCTL0); @@ -302,23 +302,23 @@ static unsigned long pll_freq_get(int pll) } else { switch (pll) { case PASS_PLL: - ret = external_clk[pa_clk]; + ret = get_external_clk(pa_clk); reg = KS2_PASSPLLCTL0; break; case TETRIS_PLL: - ret = external_clk[tetris_clk]; + ret = get_external_clk(tetris_clk); reg = KS2_ARMPLLCTL0; break; case DDR3A_PLL: - ret = external_clk[ddr3a_clk]; + ret = get_external_clk(ddr3a_clk); reg = KS2_DDR3APLLCTL0; break; case DDR3B_PLL: - ret = external_clk[ddr3b_clk]; + ret = get_external_clk(ddr3b_clk); reg = KS2_DDR3BPLLCTL0; break; case UART_PLL: - ret = external_clk[uart_clk]; + ret = get_external_clk(uart_clk); reg = KS2_UARTPLLCTL0; break; default: diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 0d8a9444de..006d0744d1 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -117,7 +117,6 @@ struct pll_init_data { int pll_od; /* PLL output divider */ }; -extern unsigned int external_clk[ext_clk_count]; extern const struct keystone_pll_regs keystone_pll_regs[]; extern s16 divn_val[]; extern int speeds[]; @@ -129,6 +128,7 @@ unsigned long ks_clk_get_rate(unsigned int clk); int get_max_dev_speed(int *spds); int get_max_arm_speed(int *spds); void pll_pa_clk_sel(void); +unsigned int get_external_clk(u32 clk); #endif #endif |