diff options
| author | Brad Griffis <bgriffis@ti.com> | 2019-04-29 09:59:29 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-05 08:48:50 -0400 |
| commit | 84cf295f8454156be70958c8dba2c1368942626e (patch) | |
| tree | 7b27483698d31d2d977826762ba0c6e3720a6321 /arch/arm/mach-omap2 | |
| parent | 82195797a415211c7a674116e40e10750237790b (diff) | |
arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error
Add 1ms delay to avoid L3 timeout error during suspend resume.
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/am33xx/ddr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 816d4e8e05..5d947a68c3 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -138,6 +138,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) /* Enable read leveling */ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + /* * Enable full read and write leveling. Wait for read and write * leveling bit to clear RDWRLVLFULL_START bit 31 |