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authorSiew Chin Lim <elly.siew.chin.lim@intel.com>2021-03-15 15:59:16 +0800
committerLey Foon Tan <ley.foon.tan@intel.com>2021-04-08 17:29:11 +0800
commitf86ed75059966e9cf1964b95850058e5a63683e4 (patch)
tree3d2c37b396944e029407a21d95e104f91231b924 /arch/arm/mach-socfpga
parent4e521e143082db6821bd3ee36f5cb990d8105253 (diff)
arm: socfpga: Move Stratix10 and Agilex SPL common code
Move Stratix10 and Agilex SPL common code to spl_soc64.c. We are in preparation for new n5x device support. No functional change in this patch. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r--arch/arm/mach-socfpga/Makefile2
-rw-r--r--arch/arm/mach-socfpga/spl_agilex.c16
-rw-r--r--arch/arm/mach-socfpga/spl_s10.c17
-rw-r--r--arch/arm/mach-socfpga/spl_soc64.c25
4 files changed, 27 insertions, 33 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 9e63296b38..e4c2da93d5 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -70,10 +70,12 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += firewall.o
obj-y += spl_s10.o
+obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
+obj-y += spl_soc64.o
endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index 71b17ce3a5..ee5a9dc1e2 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -25,22 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_mmc_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
void board_init_f(ulong dummy)
{
int ret;
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index 955a1161e8..c20e87cdbe 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -26,23 +26,6 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
-{
- /* TODO: Get from SDM or handoff */
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_mmc_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c
new file mode 100644
index 0000000000..cb98ab39e4
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ */
+
+#include <common.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT)
+u32 spl_boot_mode(const u32 boot_device)
+{
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
+ return MMCSD_MODE_FS;
+ else
+ return MMCSD_MODE_RAW;
+}
+#endif