colibri-imx8x: up-port initial implementation

USB (both host and device), Networking, MMC/SD work.

Testing:
-----------------------------------------------

U-Boot 2020.04-00119-g9dc5e94cb0-dirty (Jul 30 2020 - 22:36:54 +0300)

CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz at 47C

DRAM:  2 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
In:    serial@5a090000
Out:   serial@5a090000
Err:   serial@5a090000
Model: Toradex Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT V1.0B, Serial# 06494331
Net:   eth0: ethernet@5b040000 [PRIME]
Boot from USB for mfgtools
Hit any key to stop autoboot:  0
-----------------------------------------------

Was tested with:

imx-mkimage: imx_5.4.24_2.1.0
imx-scfw: ab182211e("Update .gitignore to ignore our built files and files from vscode")
imx-atf: imx_5.4.24_2.1.0
imx-seco: 3.6.3 [1]
-----------------------------------------------

Dropped patches from toradex_imx_v2018.03_4.14.98_2.3.0_bringup
as they have come in from mainline v2020.04 or just not relevant anymore:

9bfdda4f ("tdx-cfg-block.c: correct colibri imx8 string")
ae52342b ("colibri-imx8qxp: initial add")
9b950998 ("colibri-imx8qxp: move debug uart to lpuart3")
f9b0065b ("colibri-imx8qxp: synchronize with imx8qxp-mek from beta2")
982b4667 ("colibri-imx8qxp: forward port to 2018.03")
5c80880d ("colibri-imx8qxp: add unused pins as gpio")
30b37a6a ("colibri-imx8qxp: adjust copyright/licensing headers)
873a9561 ("colibri-imx8qxp: fix top-level compatible")
0e0f095d ("colibri-imx8qxp: clean-up device tree")
f61187df ("colibri-imx8qxp: clean-up configuration")
85a5d16b ("colibri-imx8qxp: clean-up board file")
a5a9bb4b ("colibri-imx8qxp: fused modules boot from emmc")
39c20ddd ("colibri-imx8qxp: default to dsihdmi device tree")
7443a6e5 ("colibri-imx8qxp: fix usb device/host functionality")
c721083a ("colibri-imx8qxp: fix ethernet functionality")
9f40db9d ("colibri-imx8qxp: adjust copyright/licensing headers some more")
9070b6f0 ("colibri-imx8qxp: dts: clean-up whitespace")
257470ac ("colibri-imx8x: enable FDT relocation")
a9272336 ("colibri-imx8qxp: change default device tree")
8470fb25 ("colibri-imx8x/apalis-imx8: converge scriptaddr for distroboot")
62493440 ("apalis-imx8/colibri-imx8x: use proper distroboot script")
f1993901 ("apalis-imx8/colibri-imx8x: set fdtfile since it is used by distro bootcmd")
890d03ae ("colibri-imx8qxp: sync with MEK platform")
eeb1d9b8 ("colibri-imx8qxp: move environment into first boot area")
c8c562ea ("colibri-imx8qxp: do not undef configs configured using Kconfig")
12489199 ("colibri-imx8qxp: make sure config block fdt fix-ups are called")
6a84ffaa ("colibri-imx8qxp: modify default ramdisk loading address")

[1] https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.6.3.bin

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>

2 files changed, 136 insertions, 9 deletions

diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
index 322429a98a..7b2bf7e2cd 100644
--- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
@@ -3,6 +3,30 @@
  * Copyright 2019 Toradex AG
  */
 
+/ {
+
+	aliases {
+		usbhost1 = &usbh3;
+		usbgadget0 = &usbg1;
+	};
+
+	usbh3: usbh3 {
+		compatible = "Cadence,usb3-host";
+		dr_mode = "host";
+		cdns3,usb = <&usbotg3>;
+		status = "okay";
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-pre-proper;
+	};
+
+};
+
 &{/imx8qx-pm} {
 
 	u-boot,dm-pre-proper;
@@ -72,6 +96,22 @@
 	u-boot,dm-pre-proper;
 };
 
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+	u-boot,dm-spl;
+};
+
 &pd_conn_sdch0 {
 	u-boot,dm-pre-proper;
 };
@@ -122,8 +162,30 @@
 
 &usdhc1 {
 	u-boot,dm-pre-proper;
+	/delete-property/ assigned-clock-parents;
 };
 
 &usdhc2 {
 	u-boot,dm-pre-proper;
+	/delete-property/ assigned-clock-parents;
+};
+
+&usbphy1 {
+	u-boot,dm-pre-proper;
+};
+
+&usbotg1 {
+	u-boot,dm-pre-proper;
+};
+
+&usbotg3 {
+	phys = <&usbphynop1>;
+	u-boot,dm-pre-proper;
+};
+
+&usbphynop1 {
+	compatible = "cdns,usb3-phy";
+	reg = <0x0 0x5B160000 0x0 0x40000>;
+	#phy-cells = <0>;
+	u-boot,dm-pre-proper;
 };
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts
index 0c20edf2cf..e6b01378f3 100644
--- a/arch/arm/dts/fsl-imx8qxp-colibri.dts
+++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2019 Toradex AG
+ * Copyright 2018-2019 Toradex
  */
 
 /dts-v1/;
@@ -17,22 +17,31 @@
 		stdout-path = &lpuart3;
 	};
 
-	reg_usbh_vbus: regulator-usbh-vbus {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usbh1_reg>;
-		regulator-name = "usbh_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usbh_vbus: regulator-usbh-vbus {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usbh1_reg>;
+			regulator-name = "usbh_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
+		};
 	};
+
 };
 
 &iomuxc {
+	u-boot,dm-pre-proper;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
 
 	colibri-imx8qxp {
+	u-boot,dm-pre-proper;
 		pinctrl_lpuart0: lpuart0grp {
 			fsl,pins = <
 				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
@@ -157,6 +166,7 @@
 		};
 
 		pinctrl_usdhc1: usdhc1grp {
+			u-boot,dm-pre-proper;
 			fsl,pins = <
 				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
 				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
@@ -174,6 +184,7 @@
 		};
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			u-boot,dm-pre-proper;
 			fsl,pins = <
 				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
 				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
@@ -191,6 +202,7 @@
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			u-boot,dm-pre-proper;
 			fsl,pins = <
 				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
 				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
@@ -208,12 +220,14 @@
 		};
 
 		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+			u-boot,dm-pre-proper;
 			fsl,pins = <
 				SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09	0x06000021
 			>;
 		};
 
 		pinctrl_usdhc2: usdhc2grp {
+			u-boot,dm-pre-proper;
 			fsl,pins = <
 				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
 				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
@@ -226,6 +240,7 @@
 		};
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			u-boot,dm-pre-proper;
 			fsl,pins = <
 				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
 				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
@@ -238,6 +253,7 @@
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			u-boot,dm-pre-proper;
 			fsl,pins = <
 				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
 				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
@@ -248,9 +264,27 @@
 				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
 			>;
 		};
+
+		pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
+			fsl,pins = <
+				SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
+				SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
+			>;
+		};
+
+		pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
+			fsl,pins = <
+				SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
+				SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
+			>;
+		};
 	};
 };
 
+&A35_0 {
+	u-boot,dm-pre-reloc;
+};
+
 &lpuart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart0>;
@@ -307,6 +341,24 @@
 	status = "okay";
 };
 
+&i2c0_mipi_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c0_mipi_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
 &usdhc1 {
 	bus-width = <8>;
 	non-removable;
@@ -326,3 +378,16 @@
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 	status = "okay";
 };
+
+&usbotg1 {
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg3 {
+	status = "okay";
+	vbus-supply = <&reg_usbh_vbus>;
+};