diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-05 14:33:30 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-11 21:32:44 +0100 |
| commit | 3fc9f21cdbb96d60353d6a8ad67eeca80e299cf4 (patch) | |
| tree | 57c381d6abdaa5e02c2b0bc67b490e69cfbee2d1 /arch | |
| parent | 6faac1b68e08f0d5423c24712be20ee7a7234936 (diff) | |
colibri_t20: fix l4t boot hang/errors due to clock initialisation
Fix the following boot hang observed when booting our downstream L4T
R16.5 based BSP:
[ 0.900129] kernel BUG at /build/linuxdev/oe-core_V2.7/build/tmp-
glibc/work-shared/colibri-t20/kernel-source/drivers/spi/spi-tegra.c:258!
[ 0.912478] Internal error: Oops - undefined instruction: 0 [#1]
PREEMPT SMP
[ 0.919525] Modules linked in:
[ 0.922586] CPU: 0 Not tainted (3.1.10-v2.7b1+g7e628fd #1)
[ 0.928428] PC is at spi_tegra_isr.part.0+0x14/0x18
[ 0.933310] LR is at spi_tegra_isr+0x38/0x7c
[ 0.937580] pc : [<c05c25e8>] lr : [<c0334d4c>] psr: 60000193
[ 0.937585] sp : c8075c40 ip : c8075c50 fp : c8075c4c
[ 0.949062] r10: c08a2f20 r9 : c08a2f74 r8 : 00000000
[ 0.954285] r7 : c8074000 r6 : c81545c0 r5 : c08a2f74 r4 : c81545b0
[ 0.960810] r3 : 00000000 r2 : 00000001 r1 : 60000193 r0 : 60000193
[ 0.967336] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM
Segment kernel
[ 0.974734] Control: 10c5387d Table: 0000404a DAC: 00000015
While at it also fix the following clock initialisation related errors:
[ 0.000000] tegra_dvfs: rate 216000000 too high for dvfs on sdmmc1
[ 0.000000] Unable to set clock sdmmc1 to rate 48000000: -22
[ 0.000000] tegra_dvfs: rate 216000000 too high for dvfs on sdmmc3
[ 0.000000] Unable to set clock sdmmc3 to rate 48000000: -22
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra20/clock.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index ec04cf5261..71052be1bd 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -751,6 +751,7 @@ int tegra_plle_enable(void) } struct periph_clk_init periph_clk_init_table[] = { +#ifndef CONFIG_TARGET_COLIBRI_T20 { PERIPH_ID_SPI1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, @@ -763,6 +764,7 @@ struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, +#endif /* CONFIG_TARGET_COLIBRI_T20 */ { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ }, { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH }, { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, |