diff options
| author | Stephen Warren <swarren@nvidia.com> | 2016-10-19 15:18:47 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-11-07 14:36:29 -0800 |
| commit | a8d0526133e542ea93a741fd18833e571e817775 (patch) | |
| tree | d7e39da478bc7cbaaece5f2b180ad0b410a0c372 /arch | |
| parent | 1ab557a074aaa1927f7532489a1b75137e245b70 (diff) | |
ARM: tegra186: call secure monitor for all cache-wide ops
An SMC call is required for all cache-wide operations on Tegra186. This
patch implements the two missing hooks now that U-Boot supports them, and
fixes the mapping of "hook name" to SMC call code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra186/cache.S | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra186/cache.S b/arch/arm/mach-tegra/tegra186/cache.S index 3ca3f3c8af..3061dc2ecf 100644 --- a/arch/arm/mach-tegra/tegra186/cache.S +++ b/arch/arm/mach-tegra/tegra186/cache.S @@ -9,10 +9,10 @@ #define SMC_SIP_INVOKE_MCE 0x82FFFF00 #define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) +#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14) +#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15) -ENTRY(__asm_flush_l3_dcache) - mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) - movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 +ENTRY(__asm_tegra_cache_smc) mov x1, #0 mov x2, #0 mov x3, #0 @@ -22,4 +22,22 @@ ENTRY(__asm_flush_l3_dcache) smc #0 mov x0, #0 ret +ENDPROC(__asm_invalidate_l3_dcache) + +ENTRY(__asm_invalidate_l3_dcache) + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff) + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16 + b __asm_tegra_cache_smc +ENDPROC(__asm_invalidate_l3_dcache) + +ENTRY(__asm_flush_l3_dcache) + mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff) + movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16 + b __asm_tegra_cache_smc ENDPROC(__asm_flush_l3_dcache) + +ENTRY(__asm_invalidate_l3_icache) + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 + b __asm_tegra_cache_smc +ENDPROC(__asm_invalidate_l3_icache) |