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authorStefan Agner <stefan.agner@toradex.com>2017-03-10 18:26:25 -0800
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2017-03-30 10:10:51 +0200
commit4c933fefc8ae292b31d1ce4aff9c5b34ce13fd61 (patch)
tree17ce14957d11b0df476e0f26be18c51098bdbff2 /arch
parent2f6afae9faa6a32b74cce09bfff5a82efbb8945b (diff)
ARM: vf610: add auxiliary core boot support
Use i.MX bootaux support introduced for i.MX 6SoloX/i.MX 7 for Vybrid too. Starting the Cortex-M4 core on Vybrid works a bit differently, namely it uses a GPR register to define the initial PC. There is no way to define the initial stack (the stack is set up in a boot ROM). This is not a problem for most firmwares since the firmwares startup code reinitialize the stack as part of the firmware startup code anyway. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/vf610/generic.c42
-rw-r--r--arch/arm/imx-common/Kconfig2
-rw-r--r--arch/arm/imx-common/Makefile4
-rw-r--r--arch/arm/include/asm/arch-vf610/sys_proto.h8
4 files changed, 54 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 50eb0c6b97..0456aba0d6 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -371,3 +371,45 @@ void enable_caches(void)
mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
}
#endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+#define CCM_CCOWR_START 0x00015a5a
+
+const struct memorymap hostmap[] = {
+ { .auxcore = 0x00000000, .host = 0x00000000, .size = 0x18000 },
+ { .auxcore = 0x1f000000, .host = 0x3f000000, .size = 0x80000 },
+ { .auxcore = 0x1f800000, .host = 0x1f800000, .size = 0x8000 },
+ { .auxcore = 0x3f000000, .host = 0x3f000000, .size = 0x80000 },
+ { .auxcore = 0x3f800000, .host = 0x3f800000, .size = 0x8000 },
+ { .auxcore = 0x00800000, .host = 0x80800000, .size = 0x0f800000 },
+ { .auxcore = 0x80000000, .host = 0x80000000, .size = 0xe0000000 },
+ { /* sentinel */ }
+};
+
+/* The Cortex-M4 starts from the address present in SRC_GPR2 */
+int arch_auxiliary_core_up(u32 core_id, u32 stack, u32 pc)
+{
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+
+ /* Set the PC for the Cortex-M4 */
+ writel(pc, &src->gpr2);
+
+ /* Enable M4 */
+ writel(CCM_CCOWR_START, &ccm->ccowr);
+
+ return 0;
+}
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ uint32_t val;
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+
+ val = readl(&ccm->ccowr);
+ if (val & 0x00010000)
+ return 1;
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index a6b61ad20a..f70aa30a91 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -14,7 +14,7 @@ config IMX_RDC
config IMX_BOOTAUX
bool "Support boot auxiliary core"
- depends on ARCH_MX7 || ARCH_MX6
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
help
bootaux [addr] to boot auxiliary core.
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index e59291041b..fca4d87975 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -28,9 +28,11 @@ obj-y += cache.o init.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
-obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mx7 vf610))
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
ifeq ($(SOC),$(filter $(SOC),vf610))
obj-y += ddrmc-vf610.o
endif
diff --git a/arch/arm/include/asm/arch-vf610/sys_proto.h b/arch/arm/include/asm/arch-vf610/sys_proto.h
new file mode 100644
index 0000000000..2a39816c7b
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/sys_proto.h
@@ -0,0 +1,8 @@
+/*
+ * (C) Copyright 2017
+ * Stefan Agner, Toradex
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/imx-common/sys_proto.h>