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authorMax Krummenacher <max.krummenacher@toradex.com>2017-11-05 11:50:46 +0100
committerStefan Agner <stefan.agner@toradex.com>2017-11-27 11:22:44 +0100
commit284ac523dd8e6641e12a2ca9a5b905609d78b098 (patch)
treea5b23287e31480fcaf22b9fd3999c4fe3457f794 /arch
parent8d3bb7ea495581cd8d69f0db2a4d97e2e836766b (diff)
imx: imx6ull: correct get_cpu_speed_grade_hz
backport commit 0c7c6fb7641646c45630235ea906200981f4fe80: i.MX6ULL has different speed grades than i.MX6UL. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c19
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index dc9bf3b501..0391ded149 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -114,6 +114,12 @@ u32 get_cpu_rev(void)
#define OCOTP_CFG3_SPEED_528MHZ 1
#define OCOTP_CFG3_SPEED_696MHZ 2
+/*
+ * For i.MX6ULL
+ */
+#define OCOTP_CFG3_SPEED_792MHZ 2
+#define OCOTP_CFG3_SPEED_900MHZ 3
+
u32 get_cpu_speed_grade_hz(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -126,7 +132,7 @@ u32 get_cpu_speed_grade_hz(void)
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
- if (is_mx6ul() || is_mx6ull()) {
+ if (is_mx6ul()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 528000000;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -135,6 +141,17 @@ u32 get_cpu_speed_grade_hz(void)
return 0;
}
+ if (is_mx6ull()) {
+ if (val == OCOTP_CFG3_SPEED_528MHZ)
+ return 528000000;
+ else if (val == OCOTP_CFG3_SPEED_792MHZ)
+ return 792000000;
+ else if (val == OCOTP_CFG3_SPEED_900MHZ)
+ return 900000000;
+ else
+ return 0;
+ }
+
switch (val) {
/* Valid for IMX6DQ */
case OCOTP_CFG3_SPEED_1P2GHZ: