apalis-tk1: invoking ram_repair before powerup_cpus()

Invoking tegra124_ram_repair() before powerup_cpus() is being
invoked to avoid race-conditions if arises further.
(based on downstream: fe1c9e4d523d6727afb62f03ef9fa5c0f04e7859)

Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

2 files changed, 33 insertions, 19 deletions

diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 30ae036bff..9606b420e6 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -75,29 +75,11 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id)
 	return 0;
 }
 
-static void tegra_powergate_ram_repair(void)
-{
-#ifdef CONFIG_TEGRA124
-	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
-	/* Request RAM repair for cluster 0 and wait until complete */
-	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
-	while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
-		;
-
-	/* Same for cluster 1 */
-	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
-	while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
-		;
-#endif
-}
-
 int tegra_powergate_sequence_power_up(enum tegra_powergate id,
 				      enum periph_id periph)
 {
 	int err;
 
-	tegra_powergate_ram_repair();
 	reset_set_enable(periph, 1);
 
 	err = tegra_powergate_power_on(id);
diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c
index 0aca6583ba..d5e68f252a 100644
--- a/arch/arm/mach-tegra/tegra124/cpu.c
+++ b/arch/arm/mach-tegra/tegra124/cpu.c
@@ -4,7 +4,6 @@
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
-
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/ahb.h>
@@ -105,6 +104,38 @@ static void remove_cpu_resets(void)
 	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
 }
 
+static void tegra124_ram_repair(void)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	u32 ram_repair_timeout = 500; /*usec*/
+	u32 val;
+
+	/* Request SW trigerred RAM repair by setting req  bit*/
+	/* cluster 0 */
+	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+	/* Wait for completion (status == 0) */
+	do {
+		udelay(1);
+		val = readl(&flow->ram_repair);
+	} while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--)
+		;
+
+	if (ram_repair_timeout == 0)
+		debug("Ram Repair cluster0 failed\n");
+
+	/* cluster 1 */
+	ram_repair_timeout = 500;
+	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+	/* Wait for completion (status == 0) */
+	do {
+		udelay(1);
+		val = readl(&flow->ram_repair_cluster1);
+	} while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--)
+		;
+
+	if (ram_repair_timeout == 0)
+		debug("Ram Repair cluster1 failed\n");
+}
 /**
  * Tegra124 requires some special clock initialization, including setting up
  * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
@@ -259,6 +290,7 @@ void start_cpu(u32 reset_vector)
 	clock_enable_coresight(1);
 	remove_cpu_resets();
 	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+	tegra124_ram_repair();
 	powerup_cpus();
 	debug("%s exit, should continue @ reset_vector\n", __func__);
 }