tegra: USB: Add T30 USB header files

BUG=chromium-os:23496
TEST=built Seaboard and Waluigi OK

Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I954cdb71eb80a3cf48f44b9a7183a2cafcb7755b
Reviewed-on: https://gerrit.chromium.org/gerrit/12442
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>

5 files changed, 307 insertions, 5 deletions

diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index f820581ec7..0c36fbb638 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -124,13 +124,11 @@ struct clk_rst_ctlr {
 	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX_0,      0x37C */
 	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL_0,     0x380 */
 	uint crc_reserved33[11];	/* _reserved_33,        0x384-3ac */
-
 	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
 	/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
 	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
 	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
 	struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
-
 	uint crc_reserved40[12];	/* _reserved_40,	0x450-47C */
 	uint crc_pll_cfg0;		/* _PLL_CFG0_0,		0x480 */
 	uint crc_pll_cfg1;		/* _PLL_CFG1_0,		0x484 */
@@ -242,4 +240,33 @@ enum {
 #define CLK_SYS_RATE_APB_RATE_SHIFT	0
 #define CLK_SYS_RATE_APB_RATE_MASK	(3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
 
+#if defined(CONFIG_TEGRA3)
+/* UTMIP PLL config regs moved from USB to CLK/RST domain on T30 */
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE		31:27
+#define UTMIP_PLL_SETUP_RANGE				26:18
+#define UTMIP_FORCE_PLLU_POWERUP_RANGE			17:17
+#define UTMIP_FORCE_PLLU_POWERDOWN_RANGE		16:16
+#define UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE		15:15
+#define UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE		14:14
+#define UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE		13:13
+#define UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE		12:12
+#define UTMIP_XTAL_FREQ_COUNT_RANGE			11:0
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
+#define UTMIP_PHY_XTAL_CLOCKEN_RANGE			30:30
+#define UTMIP_FORCE_PD_CLK60_POWERUP_RANGE		29:29
+#define UTMIP_FORCE_PD_CLK60_POWERDOWN_RANGE		28:28
+#define UTMIP_FORCE_PD_CLK48_POWERUP_RANGE		27:27
+#define UTMIP_FORCE_PD_CLK48_POWERDOWN_RANGE		26:26
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE		23:18
+#define UTMIP_PLLU_STABLE_COUNT_RANGE			17:6
+#define UTMIP_FORCE_PD_SAMP_C_POWERUP_RANGE		5:5
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN_RANGE		4:4
+#define UTMIP_FORCE_PD_SAMP_B_POWERUP_RANGE		3:3
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN_RANGE		2:2
+#define UTMIP_FORCE_PD_SAMP_A_POWERUP_RANGE		1:1
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN_RANGE		0:0
+#endif	/* Tegra3 */
+
 #endif	/* CLK_RST_H */
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index b7119c00b0..471420136f 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -59,9 +59,6 @@
 #define NV_PA_FUSE_BASE		0x7000F800
 #define NV_PA_CSITE_BASE	0x70040000
 
-#define NV_PA_USB1_BASE		0xC5000000
-#define NV_PA_USB3_BASE		0xC5008000
-
 #define TEGRA_SDRC_CS0		NV_PA_SDRAM_BASE
 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC
 #define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
diff --git a/arch/arm/include/asm/arch-tegra2/tegra.h b/arch/arm/include/asm/arch-tegra2/tegra.h
index 39a03e94dd..6284e22c3b 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra.h
@@ -33,6 +33,9 @@
 #define NV_PA_SDMMC3_BASE	0xC8000400
 #define NV_PA_SDMMC4_BASE	0xC8000600
 
+#define NV_PA_USB1_BASE		0xC5000000
+#define NV_PA_USB3_BASE		0xC5008000
+
 #include <asm/arch-tegra/tegra.h>
 
 #endif
diff --git a/arch/arm/include/asm/arch-tegra3/tegra.h b/arch/arm/include/asm/arch-tegra3/tegra.h
index b0baacabf3..e5308d894f 100644
--- a/arch/arm/include/asm/arch-tegra3/tegra.h
+++ b/arch/arm/include/asm/arch-tegra3/tegra.h
@@ -33,6 +33,10 @@
 #define NV_PA_SDMMC3_BASE	0x78000400
 #define NV_PA_SDMMC4_BASE	0x78000600
 
+#define NV_PA_USB1_BASE		0x7D000000
+#define NV_PA_USB2_BASE		0x7D004000
+#define NV_PA_USB3_BASE		0x7D008000
+
 #include <asm/arch-tegra/tegra.h>
 
 #endif
diff --git a/arch/arm/include/asm/arch-tegra3/usb.h b/arch/arm/include/asm/arch-tegra3/usb.h
new file mode 100644
index 0000000000..51ea2abb69
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra3/usb.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_USB_H_
+#define _TEGRA_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;   /* is this port_sc1 on some controllers? */
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint endpt_nak;
+	uint endpt_nak_enable;
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint reserved11[2];
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint reserved12[4];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint reserved15[2];
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE_RANGE		0:0
+#define NO_LEGACY_MODE				1
+
+#define VBUS_SENSE_CTL_RANGE			2:1
+#define VBUS_SENSE_CTL_VBUS_WAKEUP		0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP	1
+#define VBUS_SENSE_CTL_AB_SESS_VLD		2
+#define VBUS_SENSE_CTL_A_SESS_VLD		3
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_RANGE				31:29
+#define PTS_UTMI	0
+#define PTS_RESERVED	1
+#define PTS_ULP		2
+#define PTS_ICUSB_SER	3
+#define PTS_HSIC	4
+
+#define STS_RANGE				28:28
+#define STS_PARALLEL_IF	0
+#define STS_SERIAL_IF	1
+
+/* USB2D_USBMODE_0 */
+#define CM_RANGE				1:0
+#define CM_DEVICE_MODE				2
+#define CM_HOST_MODE				3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB_RANGE			12:12
+#define UTMIP_RESET_RANGE			11:11
+#define USB_PHY_CLK_VALID_RANGE			7:7
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE	22:22
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN_RANGE		30:30
+
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB_RANGE		24:24
+#define UTMIP_OTGPD_RANGE			11:11
+#define UTMIP_BIASPD_RANGE			10:10
+#define UTMIP_HSDISCON_LEVEL_RANGE		3:2
+#define UTMIP_HSSQUELCH_LEVEL_RANGE		1:0
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_BIAS_PDTRK_COUNT_RANGE		7:3
+#define UTMIP_FORCE_PDTRK_POWERUP_RANGE		1:1
+#define UTMIP_FORCE_PDTRK_POWERDOWN_RANGE	0:0
+
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
+#define UTMIP_DEBOUNCE_CFG0_RANGE		15:0
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J_RANGE		19:19
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG_RANGE			0:0
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL_RANGE			3:3
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_RANGE			19:15
+#define UTMIP_ELASTIC_LIMIT_RANGE		14:10
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_RANGE		4:1
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1_RANGE				3:3
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_XCVR_HSSLEW_MSB_RANGE		31:25
+#define UTMIP_XCVR_SETUP_MSB_RANGE		24:22
+#define UTMIP_XCVR_LSBIAS_SE_RANGE		21:21
+#define UTMIP_FORCE_PD_POWERDOWN_RANGE		14:14
+#define UTMIP_FORCE_PD2_POWERDOWN_RANGE		16:16
+#define UTMIP_FORCE_PDZI_POWERDOWN_RANGE	18:18
+#define UTMIP_XCVR_SETUP_RANGE			3:0
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_RANGE		21:18
+#define UTMIP_FORCE_PDDR_POWERDOWN_RANGE	4:4
+#define UTMIP_FORCE_PDCHRP_POWERDOWN_RANGE	2:2
+#define UTMIP_FORCE_PDDISC_POWERDOWN_RANGE	0:0
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS_RANGE			26:26
+
+struct ehci_hccr;
+struct ehci_hcor;
+
+/* Change the USB host port into host mode */
+void usb_set_host_mode(void);
+
+/* Setup USB on the board */
+int board_usb_init(const void *blob);
+
+/**
+ * Start up the given port number (ports are numbered from 0 on each board).
+ * This returns values for the appropriate hccr and hcor addresses to use for
+ * USB EHCI operations.
+ *
+ * @param portnum	port number to start
+ * @param hccr		returns start address of EHCI HCCR registers
+ * @param hcor		returns start address of EHCI HCOR registers
+ * @return 0 if ok, -1 on error (generally invalid port number)
+ */
+int tegrausb_start_port(unsigned portnum, struct ehci_hccr **hccr,
+	struct ehci_hcor **hcor);
+
+/**
+ * Stop the selected port
+ *
+ * @param portnum	port number to stop
+ * @return 0 if ok, -1 if no port was active
+ */
+int tegrausb_stop_port(unsigned portnum);
+
+#endif	/* _TEGRA_USB_H_ */