diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2015-06-25 17:06:17 -0300 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-09 14:42:40 +0100 |
| commit | c4f16104863ed0ab9b2a4898c230fb9eb41ea4bd (patch) | |
| tree | 60895cb04f3ba09c3b7e7758ab3cc03c67a3f574 /arch | |
| parent | b894abefad892e9de5868ead2ee5f5e582920198 (diff) | |
MLK-11201 mx7: clock: Fix PLL divider for the 100MHz case
We should divide the 1000MHz ENET PLL clock by 10 in order to achieve
100MHz, so fix the divider accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c index 39fdd75233..0bfa2e3c2f 100644 --- a/arch/arm/cpu/armv7/mx7/clock.c +++ b/arch/arm/cpu/armv7/mx7/clock.c @@ -315,7 +315,7 @@ static u32 mxc_get_pll_enet_derive(int derive) break; case PLL_ENET_MAIN_100M_CLK: if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK) - return freq / 16; + return freq / 10; break; case PLL_ENET_MAIN_50M_CLK: if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK) |