diff options
| author | Stefan Agner <stefan@agner.ch> | 2015-03-25 11:05:54 +0530 |
|---|---|---|
| committer | Stefan Agner <stefan@agner.ch> | 2015-04-14 09:08:08 +0200 |
| commit | 6f4c8c4fee6ef679e9d8fecce985e67b74ec4a8f (patch) | |
| tree | dd2a018b679871b3cd0c972ff03b5704abd60088 /arch | |
| parent | 912744734dc7066c2f394b6099c61a3f4db7cf8c (diff) | |
ARM: vf610: Enable external 32KHz oscillator
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/crm_regs.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/imx-regs.h | 11 |
2 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 724682c683..78708e22ac 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -199,6 +199,7 @@ struct anadig_reg { #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 +#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 866b30372d..aa60031b78 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -65,7 +65,7 @@ #define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) #define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) #define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) -#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) +#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) #define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) #define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) @@ -264,6 +264,9 @@ #define SRC_SRSR_WDOG_A5 (0x1 << 3) #define SRC_SRSR_POR_RST (0x1 << 0) +/* Slow Clock Source Controller Module (SCSC) */ +#define SCSC_SOSC_CTR_SOSC_EN 0x1 + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> @@ -448,6 +451,12 @@ struct mscm_ir { u16 rsvd3[848]; }; +/* SCSC */ +struct scsc_reg { + u32 sirc_ctr; + u32 sosc_ctr; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_IMX_REGS_H__ */ |