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authorDinh Nguyen <dinguyen@opensource.altera.com>2015-03-30 17:01:18 -0500
committerMarek Vasut <marex@denx.de>2015-04-21 12:23:17 +0200
commit3c38de5464b612a51b73c8b01a8f035adea7a6a4 (patch)
treee9d4708364c4aee684fef831c03b625d2974db77 /board/altera
parent9ad3a4ace27fc4bd345214e4cb3788710b428db0 (diff)
arm: socfpga: fix uart0 pin mux configuration
commit "07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK. This fixes it up so UART0 is working again. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'board/altera')
-rw-r--r--board/altera/socfpga/pinmux_config.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c
index 61cdc73fa3..7e7a18484f 100644
--- a/board/altera/socfpga/pinmux_config.c
+++ b/board/altera/socfpga/pinmux_config.c
@@ -54,8 +54,8 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
2, /* GENERALIO14 */
0, /* GENERALIO15 */
0, /* GENERALIO16 */
- 0, /* GENERALIO17 */
- 0, /* GENERALIO18 */
+ 2, /* GENERALIO17 */
+ 2, /* GENERALIO18 */
0, /* GENERALIO19 */
0, /* GENERALIO20 */
0, /* GENERALIO21 */