summaryrefslogtreecommitdiff
path: root/board/freescale
diff options
context:
space:
mode:
authorStefano Babic <sbabic@denx.de>2016-06-18 10:24:54 +0200
committerStefano Babic <sbabic@denx.de>2016-06-18 10:25:13 +0200
commitdc557e9a1fe00ca9d884bd88feef5bebf23fede4 (patch)
treeec09fdf8f7c4c44e30f4b38b7459a2cbbb71d094 /board/freescale
parentd2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4 (diff)
parent6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff)
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/b4860qds/Makefile6
-rw-r--r--board/freescale/b4860qds/ddr.c8
-rw-r--r--board/freescale/b4860qds/spl.c1
-rw-r--r--board/freescale/bsc9131rdb/Makefile16
-rw-r--r--board/freescale/bsc9132qds/Makefile9
-rw-r--r--board/freescale/c29xpcie/Makefile6
-rw-r--r--board/freescale/c29xpcie/c29xpcie.c2
-rw-r--r--board/freescale/c29xpcie/spl.c1
-rw-r--r--board/freescale/common/ls102xa_stream_id.c11
-rw-r--r--board/freescale/common/qixis.c13
-rw-r--r--board/freescale/ls1012afrdm/Kconfig15
-rw-r--r--board/freescale/ls1012afrdm/MAINTAINERS6
-rw-r--r--board/freescale/ls1012afrdm/Makefile7
-rw-r--r--board/freescale/ls1012afrdm/README58
-rw-r--r--board/freescale/ls1012afrdm/ls1012afrdm.c192
-rw-r--r--board/freescale/ls1012aqds/Kconfig15
-rw-r--r--board/freescale/ls1012aqds/MAINTAINERS6
-rw-r--r--board/freescale/ls1012aqds/Makefile7
-rw-r--r--board/freescale/ls1012aqds/README59
-rw-r--r--board/freescale/ls1012aqds/ls1012aqds.c234
-rw-r--r--board/freescale/ls1012aqds/ls1012aqds_qixis.h35
-rw-r--r--board/freescale/ls1012ardb/Kconfig15
-rw-r--r--board/freescale/ls1012ardb/MAINTAINERS6
-rw-r--r--board/freescale/ls1012ardb/Makefile7
-rw-r--r--board/freescale/ls1012ardb/README54
-rw-r--r--board/freescale/ls1012ardb/ls1012ardb.c224
-rw-r--r--board/freescale/ls1021aqds/ddr.h28
-rw-r--r--board/freescale/ls1043aqds/README37
-rw-r--r--board/freescale/ls1043aqds/ddr.c1
-rw-r--r--board/freescale/ls1043aqds/ddr.h30
-rw-r--r--board/freescale/ls1043aqds/ls1043aqds.c16
-rw-r--r--board/freescale/ls1043ardb/README37
-rw-r--r--board/freescale/ls1043ardb/cpld.c26
-rw-r--r--board/freescale/ls1043ardb/cpld.h1
-rw-r--r--board/freescale/ls1043ardb/ddr.c2
-rw-r--r--board/freescale/ls1043ardb/ddr.h9
-rw-r--r--board/freescale/ls1043ardb/ls1043ardb.c21
-rw-r--r--board/freescale/ls2080aqds/MAINTAINERS2
-rw-r--r--board/freescale/ls2080aqds/README45
-rw-r--r--board/freescale/ls2080aqds/ddr.h32
-rw-r--r--board/freescale/ls2080aqds/ls2080aqds.c2
-rw-r--r--board/freescale/ls2080ardb/MAINTAINERS2
-rw-r--r--board/freescale/ls2080ardb/README45
-rw-r--r--board/freescale/ls2080ardb/ddr.h32
-rw-r--r--board/freescale/ls2080ardb/ls2080ardb.c6
-rw-r--r--board/freescale/m5329evb/nand.c2
-rw-r--r--board/freescale/m5373evb/nand.c2
-rw-r--r--board/freescale/mpc5121ads/mpc5121ads.c4
-rw-r--r--board/freescale/p1010rdb/Makefile12
-rw-r--r--board/freescale/p1010rdb/spl.c1
-rw-r--r--board/freescale/p1022ds/Makefile12
-rw-r--r--board/freescale/p1022ds/spl.c1
-rw-r--r--board/freescale/p1_p2_rdb_pc/Makefile17
-rw-r--r--board/freescale/p1_p2_rdb_pc/spl.c1
-rw-r--r--board/freescale/p2041rdb/Makefile2
-rw-r--r--board/freescale/t102xqds/Makefile2
-rw-r--r--board/freescale/t102xqds/ddr.c27
-rw-r--r--board/freescale/t102xqds/spl.c1
-rw-r--r--board/freescale/t102xrdb/Makefile2
-rw-r--r--board/freescale/t102xrdb/ddr.c16
-rw-r--r--board/freescale/t102xrdb/spl.c1
-rw-r--r--board/freescale/t1040qds/ddr.h22
-rw-r--r--board/freescale/t104xrdb/ddr.c7
-rw-r--r--board/freescale/t104xrdb/ddr.h26
-rw-r--r--board/freescale/t104xrdb/spl.c1
-rw-r--r--board/freescale/t208xqds/MAINTAINERS2
-rw-r--r--board/freescale/t208xqds/Makefile6
-rw-r--r--board/freescale/t208xqds/ddr.c5
-rw-r--r--board/freescale/t208xqds/ddr.h40
-rw-r--r--board/freescale/t208xqds/spl.c1
-rw-r--r--board/freescale/t208xrdb/MAINTAINERS2
-rw-r--r--board/freescale/t208xrdb/Makefile6
-rw-r--r--board/freescale/t208xrdb/ddr.c6
-rw-r--r--board/freescale/t208xrdb/ddr.h20
-rw-r--r--board/freescale/t208xrdb/spl.c1
-rw-r--r--board/freescale/t4qds/Makefile6
-rw-r--r--board/freescale/t4qds/ddr.c7
-rw-r--r--board/freescale/t4qds/ddr.h38
-rw-r--r--board/freescale/t4qds/spl.c1
-rw-r--r--board/freescale/t4rdb/Makefile9
-rw-r--r--board/freescale/t4rdb/ddr.c5
-rw-r--r--board/freescale/t4rdb/ddr.h38
-rw-r--r--board/freescale/t4rdb/eth.c5
-rw-r--r--board/freescale/t4rdb/spl.c1
84 files changed, 1280 insertions, 465 deletions
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
index 0acd2a9aa4..673d2ea56a 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -5,11 +5,11 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
obj-y += b4860qds.o
-obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_B4860QDS) += eth_b4860qds.o
+obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index eb10a6f364..31b186ea8c 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -179,15 +179,13 @@ phys_size_t initdram(int board_type)
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
#else
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
return dram_size;
}
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
index 3f7cc03581..fabc78301a 100644
--- a/board/freescale/b4860qds/spl.c
+++ b/board/freescale/b4860qds/spl.c
@@ -91,6 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
index b26d3a1e63..8027750efb 100644
--- a/board/freescale/bsc9131rdb/Makefile
+++ b/board/freescale/bsc9131rdb/Makefile
@@ -13,15 +13,11 @@ endif
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
-
-obj-y += bsc9131rdb.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-#obj-y += bsc9131rdb_mux.o
-
+obj-y += bsc9131rdb.o
+obj-y += ddr.o
endif
+
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
index 2e4170f512..54193350af 100644
--- a/board/freescale/bsc9132qds/Makefile
+++ b/board/freescale/bsc9132qds/Makefile
@@ -13,14 +13,11 @@ endif
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
-
obj-y += bsc9132qds.o
obj-y += ddr.o
+endif
+
obj-y += law.o
obj-y += tlb.o
-
-endif
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 818484a57d..93b3cba031 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -11,15 +11,15 @@ endif
endif
ifdef MINIMAL
-obj-y += spl_minimal.o tlb.o law.o
+obj-y += spl_minimal.o
else
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif
-
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
+endif
+
obj-y += law.o
obj-y += tlb.o
-endif
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index e325b4db4a..45f463f01f 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset)
while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
- + offset * 0x20000)) >= 0) {
+ + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
fdt_del_node(blob, nodeoff);
offset++;
}
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
index 3d31d41a4f..d8d73c70b8 100644
--- a/board/freescale/c29xpcie/spl.c
+++ b/board/freescale/c29xpcie/spl.c
@@ -57,6 +57,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
/* relocate environment function pointers etc. */
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index f43426991b..0abaffb334 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -10,11 +10,14 @@
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
- uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+ void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
int i;
+ u32 icid;
- for (i = 0; i < num; i++)
- out_be32(scfg + id[i].offset, id[i].stream_id);
+ for (i = 0; i < num; i++) {
+ icid = (id[i].stream_id & 0xff) << 24;
+ out_be32((u32 *)(scfg + id[i].offset), icid);
+ }
}
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
@@ -28,6 +31,6 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
else
liodn = tbl[i].id[0];
- out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
+ out_le32((u32 *)(tbl[i].reg_offset), liodn);
}
}
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f64a..0db0ed6670 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -14,6 +14,13 @@
#include <i2c.h>
#include "qixis.h"
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
@@ -27,6 +34,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
}
#endif
+#ifdef QIXIS_BASE
u8 qixis_read(unsigned int reg)
{
void *p = (void *)QIXIS_BASE;
@@ -40,6 +48,7 @@ void qixis_write(unsigned int reg, u8 value)
out_8(p + reg, value);
}
+#endif
u16 qixis_read_minor(void)
{
@@ -142,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
{
u8 reg;
- reg = QIXIS_READ(brdcfg[0]);
+ reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
- QIXIS_WRITE(brdcfg[0], reg);
+ QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
}
static void __maybe_unused set_rcw_src(int rcw_src)
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 0000000000..a34521cf79
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+ default "ls1012afrdm"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012afrdm"
+
+endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644
index 0000000000..842f86f861
--- /dev/null
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012afrdm/
+F: include/configs/ls1012afrdm.h
+F: configs/ls1012afrdm_qspi_defconfig
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
new file mode 100644
index 0000000000..dbfa2cea38
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
new file mode 100644
index 0000000000..181c4615a8
--- /dev/null
+++ b/board/freescale/ls1012afrdm/README
@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+ - 2 SGMII 1G PHYs
+ - DDR Controller
+ - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ operating at 1.35 V
+ - QSPI
+ - Onboard 512 Mbit QSPI flash memory running at speed up
+ to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+ - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+ Micro-AB connector.
+ - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+ as a Micro-AB device.
+ - I2C controller
+ - One I2C bus with connectivity to Arduino headers
+ - UART
+ - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+ - ARM Cortex® 10-pin JTAG connector for LS1012A
+ - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+ - One SAI port, SAI 2 with full duplex support
+ - Clocks
+ - 25 MHz crystal for LS1012A
+ - 8 MHz Crystal for K20
+ - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+ - 5 V input supply from USB
+ - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+ other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644
index 0000000000..a94a458f53
--- /dev/null
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ puts("Board: LS1012AFRDM ");
+
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
new file mode 100644
index 0000000000..1257ec8d06
--- /dev/null
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+ default "ls1012aqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012aqds"
+
+endif
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
new file mode 100644
index 0000000000..27c4affd30
--- /dev/null
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012aqds/
+F: include/configs/ls1012aqds.h
+F: configs/ls1012aqds_qspi_defconfig
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
new file mode 100644
index 0000000000..0b813f9784
--- /dev/null
+++ b/board/freescale/ls1012aqds/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012aqds.o
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
new file mode 100644
index 0000000000..dee4b302c1
--- /dev/null
+++ b/board/freescale/ls1012aqds/README
@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+ - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+ emulator
+ - USB 3.0
+ - One USB 3.0 controller with integrated PHY
+ - One high-speed USB 3.0 port
+ - USB 2.0
+ - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+ - SDHC1 controller can be connected to onboard SDHC connector
+ - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+ - One SAI port with audio codec SGTL5000:
+ • Provides MIC bias
+ • Provides headphone and line output
+ - One SAI port terminated at 2x6 header
+ - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
new file mode 100644
index 0000000000..71eea82a03
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+
+ sw = QIXIS_READ(arch);
+ printf("Board Arch: V%d, ", sw >> 4);
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+ sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+ if (sw & QIXIS_LBMAP_ALTBANK)
+ printf("flash: 2\n");
+ else
+ printf("flash: 1\n");
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ u8 mux_sdhc_cd = 0x80;
+
+ i2c_set_bus_num(0);
+
+ i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+ CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to enable barrier
+ * transaction */
+ out_le32(&cci->ctrl_ord,
+ CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
new file mode 100644
index 0000000000..584f604aa8
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xe0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100 0x0
+#define QIXIS_SDCLK1_125 0x1
+#define QIXIS_SDCLK1_165 0x2
+#define QIXIS_SDCLK1_100_SP 0x3
+
+#endif
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
new file mode 100644
index 0000000000..3f67c2841f
--- /dev/null
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+ default "ls1012ardb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012ardb"
+
+endif
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
new file mode 100644
index 0000000000..79a2a7dd24
--- /dev/null
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012ARDB BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012ardb/
+F: include/configs/ls1012ardb.h
+F: configs/ls1012ardb_qspi_defconfig
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
new file mode 100644
index 0000000000..05fa9d9c5b
--- /dev/null
+++ b/board/freescale/ls1012ardb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012ardb.o
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
new file mode 100644
index 0000000000..453b432915
--- /dev/null
+++ b/board/freescale/ls1012ardb/README
@@ -0,0 +1,54 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012ARDB board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+ - QSPI NOR flash memory (2 virtual banks)
+ - the QSPI emulator.s
+ - USB 3.0
+ - one high-speed USB 2.0/3.0 port.
+ - Two enhanced secure digital host controllers:
+ - SDHC1 controller can be connected to onboard SDHC connector
+ - SDHC2 controller: Three dual 1:4 mux/demux devices,
+ 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
+ SDIO WiFi, SPI, and Ardiuno shield
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - The LS1012A processor consists of two UART controllers,
+ out of which only UART1 is used on RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
new file mode 100644
index 0000000000..f69768d24e
--- /dev/null
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ u8 in1;
+
+ puts("Board: LS1012ARDB ");
+
+ /* Initialize i2c early for Serial flash bank information */
+ i2c_set_bus_num(0);
+
+ if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+ printf("Error reading i2c boot information!\n");
+ return 0; /* Don't want to hang() on this error */
+ }
+
+ puts("Version");
+ if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+ puts(": RevA");
+ else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+ puts(": RevB");
+ else
+ puts(": unknown");
+
+ printf(", boot from QSPI");
+ if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+ puts(": emu\n");
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+ puts(": bank1\n");
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+ puts(": bank2\n");
+ else
+ puts("unknown\n");
+
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
index f819c99dba..b39b561dc1 100644
--- a/board/freescale/ls1021aqds/ddr.h
+++ b/board/freescale/ls1021aqds/ddr.h
@@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,},
- {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
- {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,},
+ {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
+ {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
- {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
index a6fd7a35f5..913537d451 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -8,41 +8,8 @@ debugging environment.
LS1043A SoC Overview
--------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
- the following functions:
- - Packet parsing, classification, and distribution (FMan)
- - Queue management for scheduling, packet sequencing, and congestion
- management (QMan)
- - Hardware buffer management for buffer allocation and de-allocation (BMan)
- - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
- - Up to 1 x QSGMII
- - Up to 4 x SGMII supporting 1000Mbps
- - Up to 2 x SGMII supporting 2500Mbps
- - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
- - Three PCIe 2.0 controllers, one supporting x4 operation
- - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
- - Three high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Serial peripheral interface (SPI) controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
LS1043AQDS board Overview
-----------------------
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 3d3c53385a..0fd835d74f 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -116,6 +116,7 @@ phys_size_t initdram(int board_type)
dram_size = fsl_ddr_sdram();
#endif
+ erratum_a008850_post();
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();
diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h
index 8adb660012..ad709ba216 100644
--- a/board/freescale/ls1043aqds/ddr.h
+++ b/board/freescale/ls1043aqds/ddr.h
@@ -7,6 +7,8 @@
#ifndef __DDR_H__
#define __DDR_H__
+extern void erratum_a008850_post(void);
+
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
@@ -32,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,},
- {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
- {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,},
+ {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
+ {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
- {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
- {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
- {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index fba6b88951..7e47ef0d82 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -238,8 +238,8 @@ int board_early_init_f(void)
out_be32(&scfg->rcwpmuxcr0, 0x3333);
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
usb_pwrfault =
- (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
- (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
#endif
@@ -307,14 +307,6 @@ int misc_init_r(void)
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
- CONFIG_SYS_CCI400_ADDR;
-
- /* Set CCI-400 control override register to enable barrier
- * transaction */
- out_le32(&cci->ctrl_ord,
- CCI400_CTRLORD_EN_BARRIER);
-
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
@@ -325,10 +317,6 @@ int board_init(void)
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
-
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
return 0;
}
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
index 0556e73b3a..709ddbbef3 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
LS1043A SoC Overview
--------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
- the following functions:
- - Packet parsing, classification, and distribution (FMan)
- - Queue management for scheduling, packet sequencing, and congestion
- management (QMan)
- - Hardware buffer management for buffer allocation and de-allocation (BMan)
- - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
- - Up to 1 x QSGMII
- - Up to 4 x SGMII supporting 1000Mbps
- - Up to 2 x SGMII supporting 2500Mbps
- - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
- - Three PCIe 2.0 controllers, one supporting x4 operation
- - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
- - Three high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Serial peripheral interface (SPI) controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
LS1043ARDB board Overview
-----------------------
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 78c28246a8..c6452830ed 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value)
/* Set the boot bank to the alternate bank */
void cpld_set_altbank(void)
{
+ u16 reg = CPLD_CFG_RCW_SRC_NOR;
u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
u8 reg7 = CPLD_READ(vbank);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+ cpld_rev_bit(&reg5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void)
/* Set the boot bank to the default bank */
void cpld_set_defbank(void)
{
- CPLD_WRITE(global_rst, 1);
+ u16 reg = CPLD_CFG_RCW_SRC_NOR;
+ u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(&reg5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(vbank, 0);
+
+ CPLD_WRITE(system_rst, 1);
}
void cpld_set_nand(void)
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
index bd59c0e5d5..cb175b56fa 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value);
#define CPLD_SW_MUX_BANK_SEL 0x40
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_SEL_ALTBANK 0x04
+#define CPLD_CFG_RCW_SRC_NOR 0x025
#define CPLD_CFG_RCW_SRC_NAND 0x106
#define CPLD_CFG_RCW_SRC_SD 0x040
#endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 11bc0f24d9..1e2fd2ed0c 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -177,6 +177,8 @@ phys_size_t initdram(int board_type)
#else
dram_size = fsl_ddr_sdram_size();
#endif
+ erratum_a008850_post();
+
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();
#endif
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
index b17eb80885..a77ddf3d24 100644
--- a/board/freescale/ls1043ardb/ddr.h
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -6,6 +6,9 @@
#ifndef __DDR_H__
#define __DDR_H__
+
+extern void erratum_a008850_post(void);
+
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
@@ -31,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,},
- {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,},
- {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,},
+ {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
+ {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
+ {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
#endif
{}
};
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index ec5fdbfe27..14365207da 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -19,7 +19,6 @@
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <environment.h>
#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
@@ -31,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
- static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+ static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
- u32 cfg_rcw_src;
+ u16 cfg_rcw_src;
#endif
- u32 sd1refclk_sel;
+ u8 sd1refclk_sel;
printf("Board: LS1043ARDB, boot from ");
@@ -83,22 +82,12 @@ int board_early_init_f(void)
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
- /*
- * Set CCI-400 control override register to enable barrier
- * transaction
- */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_FSL_IFC
init_final_memctl_regs();
#endif
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
@@ -106,6 +95,8 @@ int board_init(void)
#ifdef CONFIG_U_QE
u_qe_init();
#endif
+ /* invert AQR105 IRQ pins polarity */
+ out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
return 0;
}
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 7d3bfc8e4e..076532622f 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
F: board/freescale/ls2080a/ls2080aqds.c
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 6ddad92f2c..5c98866712 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with
a complete debugging environment.
LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
- the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
- - Packet parsing, classification, and distribution (WRIOP)
- - Queue and Hardware buffer management for scheduling, packet sequencing, and
- congestion management, buffer allocation and de-allocation (QBMan)
- - Cryptography acceleration (SEC) at up to 10 Gbps
- - RegEx pattern matching acceleration (PME) at up to 10 Gbps
- - Decompression/compression acceleration (DCE) at up to 20 Gbps
- - Accelerated I/O processing (AIOP) at up to 20 Gbps
- - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
- - Up to eight 10 Gbps Ethernet MACs
- - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
- - Two serial ATA (SATA 3.0) controllers
- - Two high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Serial peripheral interface (SPI) controller
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
- capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
LS2080AQDS board Overview
-----------------------
diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h
index b76ea61ba0..eba62c33b2 100644
--- a/board/freescale/ls2080aqds/ddr.h
+++ b/board/freescale/ls2080aqds/ddr.h
@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
- {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40afb7..897793d85b 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
+#ifdef CONFIG_FSL_MC_ENET
int err;
+#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 5562917ec9..a20c003ce7 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls2080ardb/
F: board/freescale/ls2080a/ls2080ardb.c
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 6708ca9cc7..b1613ba680 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
- the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
- - Packet parsing, classification, and distribution (WRIOP)
- - Queue and Hardware buffer management for scheduling, packet sequencing, and
- congestion management, buffer allocation and de-allocation (QBMan)
- - Cryptography acceleration (SEC) at up to 10 Gbps
- - RegEx pattern matching acceleration (PME) at up to 10 Gbps
- - Decompression/compression acceleration (DCE) at up to 20 Gbps
- - Accelerated I/O processing (AIOP) at up to 20 Gbps
- - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
- - Up to eight 10 Gbps Ethernet MACs
- - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
- - Two serial ATA (SATA 3.0) controllers
- - Two high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Serial peripheral interface (SPI) controller
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
- capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
LS2080ARDB board Overview
-----------------------
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index bda9d4a40f..8d5a49061c 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
- {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
- {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,},
+ {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,},
+ {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,},
{}
};
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
- {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
{}
};
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
{}
};
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index fb39af6445..52e5e3f516 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -156,7 +156,9 @@ int board_init(void)
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+#ifdef CONFIG_FSL_MC_ENET
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
u32 val;
init_final_memctl_regs();
@@ -178,8 +180,10 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
+#ifdef CONFIG_FSL_MC_ENET
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
return 0;
}
@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
+#ifdef CONFIG_FSL_MC_ENET
int err;
+#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 8d88bc03c0..88496812bf 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index 92cef2a97d..a96a59991f 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtdinfo->priv;
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 40bd55dfba..7c44282ca2 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -274,11 +274,11 @@ int checkboard (void)
return 0;
}
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index 660d1bbc2a..86eb6946dd 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -13,18 +13,14 @@ endif
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
-
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
endif
-
obj-y += p1010rdb.o
obj-y += ddr.o
+endif
+
obj-y += law.o
obj-y += tlb.o
-
-endif
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index eb8e567554..f8584084ce 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -72,6 +72,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index a5821277ef..9793853463 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -13,17 +13,15 @@ endif
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
endif
obj-y += p1022ds.o
obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-
obj-$(CONFIG_FSL_DIU_FB) += diu.o
endif
+
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 89ef95aab8..04db767f98 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -86,6 +86,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
#endif
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index a2a1f92ce8..045d4093ae 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -13,17 +13,14 @@ endif
endif
ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
+obj-y += spl_minimal.o
else
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
endif
-
-obj-y += p1_p2_rdb_pc.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-
+obj-y += p1_p2_rdb_pc.o
+obj-y += ddr.o
endif
+
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 0142746c84..76a3cf47cc 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -83,6 +83,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
index c74f4c62f8..a335ec65fa 100644
--- a/board/freescale/p2041rdb/Makefile
+++ b/board/freescale/p2041rdb/Makefile
@@ -7,6 +7,6 @@
#
obj-y += p2041rdb.o
-obj-y += cpld.o
+obj-y += cpld.o
obj-y += ddr.o
obj-y += eth.o
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
index d94f2307d9..afbc9146ed 100644
--- a/board/freescale/t102xqds/Makefile
+++ b/board/freescale/t102xqds/Makefile
@@ -5,7 +5,7 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
obj-y += t102xqds.o
obj-y += eth_t102xqds.o
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 2d4d10f351..c26f3503b9 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#if defined(CONFIG_SYS_FSL_DDR4)
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif
@@ -172,14 +172,13 @@ phys_size_t initdram(int board_type)
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
index 073ff2dcde..d59d3431ec 100644
--- a/board/freescale/t102xqds/spl.c
+++ b/board/freescale/t102xqds/spl.c
@@ -120,6 +120,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index 052006610e..64528656ac 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -5,7 +5,7 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
obj-y += t102xrdb.o
obj-$(CONFIG_T1024RDB) += cpld.o
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index adf9fd5f78..edfbdbf3a8 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{}
};
@@ -234,12 +234,12 @@ phys_size_t initdram(int board_type)
puts("Initializing....using SPD\n");
#endif
dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index da97c440c4..bd3cbbf11c 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -107,6 +107,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
index a6e1673525..1e087460cb 100644
--- a/board/freescale/t1040qds/ddr.h
+++ b/board/freescale/t1040qds/ddr.h
@@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
- {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index cf79d2ddb2..22d6a5f617 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -124,15 +124,12 @@ phys_size_t initdram(int board_type)
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
#else
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index b9c02f7fe0..012991cf46 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2
*/
#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a},
+ {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a},
#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
- {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
- {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
- {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
- {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
- {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
- {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
- {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
- {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
- {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
- {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
- {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {2, 833, 4, 8, 6, 0x06060607, 0x08080807},
+ {2, 833, 0, 8, 6, 0x06060607, 0x08080807},
+ {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
+ {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
+ {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
+ {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
+ {1, 833, 4, 8, 6, 0x06060607, 0x08080807},
+ {1, 833, 0, 8, 6, 0x06060607, 0x08080807},
+ {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
+ {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
+ {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
+ {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
#else
#error DDR type not defined
#endif
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 81f48c4c30..4b35af63f6 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -98,6 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
index deda092a6a..d747de3f34 100644
--- a/board/freescale/t208xqds/MAINTAINERS
+++ b/board/freescale/t208xqds/MAINTAINERS
@@ -1,5 +1,5 @@
T208XQDS BOARD
-#M: -
+M: Shengzhou Liu <Shengzhou.Liu@nxp.com>
S: Maintained
F: board/freescale/t208xqds/
F: include/configs/T208xQDS.h
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
index 6cb72c9fd5..ef04a26463 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -7,10 +7,8 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_T2080QDS) += t208xqds.o
-obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
-obj-$(CONFIG_T2081QDS) += t208xqds.o
-obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
index f1aff5481e..f96470f020 100644
--- a/board/freescale/t208xqds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
@@ -108,13 +108,12 @@ phys_size_t initdram(int board_type)
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
return dram_size;
}
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
index 9c26fdf3bd..255ab2c543 100644
--- a/board/freescale/t208xqds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
@@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09},
- {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a},
- {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c},
- {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d},
- {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d},
- {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
- {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
- {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c},
- {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09},
+ {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a},
+ {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c},
+ {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d},
+ {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d},
+ {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c},
+ {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
@@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = {
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
/* TODO: need tuning these parameters if RDIMM is used */
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
{}
};
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index 55a0f8fdce..bb02dab2f1 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -106,6 +106,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
index 16428798cd..ccbfbab142 100644
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -1,5 +1,5 @@
T208XRDB BOARD
-#M: -
+M: Shengzhou Liu <Shengzhou.Liu@nxp.com>
S: Maintained
F: board/freescale/t208xrdb/
F: include/configs/T208xRDB.h
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index 9605f8b606..cd8fe096d8 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -5,11 +5,9 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
-obj-$(CONFIG_T2080RDB) += t208xrdb.o
-obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
-obj-$(CONFIG_T2080RDB) += cpld.o
+obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index 053f128e5b..f6c8ca30ac 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -101,12 +101,12 @@ phys_size_t initdram(int board_type)
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
return dram_size;
}
diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h
index 08cbb606d5..175cf56a09 100644
--- a/board/freescale/t208xrdb/ddr.h
+++ b/board/freescale/t208xrdb/ddr.h
@@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
- {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
- {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {2, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
- {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
- {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
- {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09},
+ {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
+ {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
+ {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
+ {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
{}
};
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index f63366bb0e..2ff05a29f5 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -76,6 +76,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index bd2c1f1622..731ccb0b29 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -5,12 +5,12 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
-obj-$(CONFIG_T4240QDS) += t4240qds.o
-obj-$(CONFIG_T4240QDS)+= eth.o
+obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o
obj-$(CONFIG_PCI) += pci.o
endif
+
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 62d58c5b1f..d533924a0d 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -117,13 +117,12 @@ phys_size_t initdram(int board_type)
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
return dram_size;
}
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index 4d0e3c497d..0b0cc9af39 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
@@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
+ {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{}
};
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
index d52059a145..6ca0f03ffe 100644
--- a/board/freescale/t4qds/spl.c
+++ b/board/freescale/t4qds/spl.c
@@ -116,6 +116,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 83b55ee193..4f29eea0f4 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -5,13 +5,14 @@
#
ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y += spl.o
else
-obj-$(CONFIG_T4240RDB) += t4240rdb.o
-obj-y += cpld.o
-obj-y += eth.o
+obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += cpld.o
+obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
endif
+
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 27b37b5cc4..230f031a3b 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -110,13 +110,12 @@ phys_size_t initdram(int board_type)
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
return dram_size;
}
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
index 7b854767e7..f01ebb22b5 100644
--- a/board/freescale/t4rdb/ddr.h
+++ b/board/freescale/t4rdb/ddr.h
@@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
- {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
- {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
- {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
- {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
- {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
- {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
+ {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
+ {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
+ {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
+ {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
+ {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
+ {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
+ {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
+ {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
+ {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
{}
};
@@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
- {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
- {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
- {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
- {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
- {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
- {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
{}
};
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index e563a6169a..ae2451e4ba 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -77,6 +77,9 @@ int board_eth_init(bd_t *bis)
puts("Invalid SerDes1 protocol for T4240RDB\n");
}
+ fm_disable_port(FM1_DTSEC5);
+ fm_disable_port(FM1_DTSEC6);
+
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
@@ -115,6 +118,8 @@ int board_eth_init(bd_t *bis)
puts("Invalid SerDes2 protocol for T4240RDB\n");
}
+ fm_disable_port(FM2_DTSEC5);
+ fm_disable_port(FM2_DTSEC6);
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 4c1e0cc8d0..b148a7fd1f 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -80,6 +80,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,