diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-03-09 10:19:33 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-05-09 16:06:58 +0800 |
| commit | a1c1aa1892238ead49e99478472dc9c743510d56 (patch) | |
| tree | bcbd7c00147a0a31fed3bd01fdabc3136b8cd59e /board/freescale | |
| parent | a0e830308539e1afe19a0e15ea04e4ca341a1304 (diff) | |
MLK-23654 board: imx8mm_val: enable the ddr3l multi-setpoint support on imx8mm
Enable the multi-setpoint support for imx8mm ddr3l val board.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 2978984c8d3c7ace8017459266eb7bdd7a17e2d1)
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/imx8mm_val/ddr3l_timing.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/imx8mm_val/ddr3l_timing.c b/board/freescale/imx8mm_val/ddr3l_timing.c index 3aa4077682..467476d788 100644 --- a/board/freescale/imx8mm_val/ddr3l_timing.c +++ b/board/freescale/imx8mm_val/ddr3l_timing.c @@ -156,7 +156,7 @@ struct dram_cfg_param ddr3l_ddrc_cfg[] = { { DDRC_FREQ2_ODTCFG(0), 0x04050800 }, /* default start freq point */ - { DDRC_MSTR2(0), 0x0}, + { DDRC_MSTR2(0), 0x2}, }; /* PHY Initialize Configuration */ @@ -320,7 +320,6 @@ struct dram_cfg_param ddr3l_ddrphy_cfg[] = { { 0x200f6, 0x5555 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x20060, 0x2 }, }; /* ddr phy trained CSR */ @@ -1351,7 +1350,7 @@ struct dram_fsp_msg ddr3l_dram_fsp_msg[] = { .fsp_cfg = ddr3l_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp0_cfg), }, -#if 0 +#if 1 { /* P1 1066mts 1D */ .drate = 1066, @@ -1381,4 +1380,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr3l_ddrphy_trained_csr), .ddrphy_pie = ddr3l_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr3l_phy_pie), + .fsp_table = { 1600, 1066, 667 }, }; |