diff options
| author | Ye Li <ye.li@nxp.com> | 2020-11-05 23:09:51 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2020-11-08 18:37:00 -0800 |
| commit | ba50b01b74873cbddaeba61f69e7763a8ba63227 (patch) | |
| tree | 6232b6e6acca1ace5b6f45291566860d9e4b4563 /board/freescale | |
| parent | 5d556b8e214739deb5c3c71efa2ea8fc28f2a643 (diff) | |
MLK-24971-2 imx8mp_evk: Set GIC clock to 500Mhz on LPDDR4 EVK only
Since iMX8MP LPDDR4 EVK uses OD for VDD_SOC, so we can set GIC clock
to 500Mhz to align with kernel. For DDR4 EVK, uses default 400Mhz for
ND VDD_SOC.
Move the codes from SOC codes to board level to match with voltage
setting.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/imx8mp_evk/spl.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 4cb6385bc4..a26bc85633 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -218,6 +218,16 @@ int power_init_board(void) void spl_board_init(void) { + /* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it. + * Should set the clock after PMIC setting done. + * Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC + */ +#ifdef CONFIG_IMX8M_LPDDR4 + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); +#endif + puts("Normal Boot\n"); } |