diff options
| author | Ye Li <ye.li@nxp.com> | 2020-11-18 19:03:13 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2020-11-18 21:44:18 -0800 |
| commit | ce4ac958be9393d01e63bfeddb43e58db929c24e (patch) | |
| tree | fc38f449d3d9a30182823fb07df7783e6c69c6a7 /board/freescale | |
| parent | f8b6a0ea9371ea8d5a3c4c6216510b4052302656 (diff) | |
LF-2769-1 mx7dsabresd: Reserve top 1MB DDR for RPMSG usage
When booting with M4 RPMSG demo in u-boot, the M4 will use top 1MB
DDR for RPMSG vring buffer. This overlaps with u-boot MMU table and
modifies some MMU entries.
On mx7dsabresd, this cause u-boot failed to access LCDIF registers
due to the wrong MMU entries.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 8a03d17c92cc04765c6b93f716ea081486fd15f0)
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx7dsabresd/mx7dsabresd.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 1f7196719b..603b32ee76 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -226,6 +226,14 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +#ifdef CONFIG_IMX_BOOTAUX +ulong board_get_usable_ram_top(ulong total_size) +{ + /* Reserve top 1M memory used by M core vring/buffer */ + return gd->ram_top - SZ_1M; +} +#endif + #ifdef CONFIG_FEC_MXC static int setup_fec(void) { |