ppc4xx: Add Io and IoCon 405EP board support

Board support for the Guntermann & Drunck CATCenter Io.
Board support for the Guntermann & Drunck IoCon.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>

4 files changed, 564 insertions, 0 deletions

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
new file mode 100644
index 0000000000..d3bd233094
--- /dev/null
+++ b/board/gdsys/405ep/405ep.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+int board_early_init_f(void)
+{
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 * -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+
+	/*
+	 * setup io-latches for reset
+	 */
+	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+
+	/*
+	 * wait for fpga-done
+	 * fail ungraceful if fpga is not configuring properly
+	 */
+	while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
+		;
+
+	/*
+	 * setup io-latches for boot (stop reset)
+	 */
+	udelay(10);
+	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+
+	/*
+	 * wait for fpga out of reset
+	 * fail ungraceful if fpga is not working properly
+	 */
+	while (1) {
+		fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
+		if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
+			REFLECTION_TESTPATTERN_INV)
+			break;
+	}
+
+	return 0;
+}
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
new file mode 100644
index 0000000000..13dff52d77
--- /dev/null
+++ b/board/gdsys/405ep/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-$(CONFIG_IO) += io.o
+COBJS-$(CONFIG_IOCON) += iocon.o
+
+COBJS   := $(BOARD).o $(COBJS-y)
+SOBJS   =
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
new file mode 100644
index 0000000000..80877b61ff
--- /dev/null
+++ b/board/gdsys/405ep/io.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <miiphy.h>
+
+#include "../common/fpga.h"
+
+#define PHYREG_CONTROL				0
+#define PHYREG_PAGE_ADDRESS			22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
+
+enum {
+	REG_VERSIONS = 0x0002,
+	REG_FPGA_FEATURES = 0x0004,
+	REG_FPGA_VERSION = 0x0006,
+	REG_QUAD_SERDES_RESET = 0x0012,
+};
+
+enum {
+	UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_121 = 2,
+	HWVER_122 = 3,
+};
+
+int configure_gbit_phy(unsigned char addr)
+{
+	unsigned short value;
+
+	/* select page 2 */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PAGE_ADDRESS, 0x0002))
+		goto err_out;
+	/* disable SGMII autonegotiation */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
+		goto err_out;
+	/* select page 0 */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PAGE_ADDRESS, 0x0000))
+		goto err_out;
+	/* switch from powerdown to normal operation */
+	if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
+		goto err_out;
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
+		goto err_out;
+	/* reset phy so settings take effect */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_CONTROL, 0x9140))
+		goto err_out;
+
+	return 0;
+
+err_out:
+	printf("Error writing to the PHY addr=%02x\n", addr);
+	return -1;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u16 versions = fpga_get_reg(REG_VERSIONS);
+	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_channels;
+	unsigned feature_expansion;
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_channels = fpga_features & 0x007f;
+	feature_expansion = fpga_features & (1<<15);
+
+	printf("Board: ");
+
+	printf("CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	switch (unit_type) {
+	case UNITTYPE_CCD_SWITCH:
+		printf("CCD-Switch");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	case HWVER_121:
+		printf(" HW-Ver 1.21\n");
+		break;
+
+	case HWVER_122:
+		printf(" HW-Ver 1.22\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %d channel(s)", feature_channels);
+
+	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+
+	return 0;
+}
+
+/*
+ * setup Gbit PHYs
+ */
+int last_stage_init(void)
+{
+	unsigned int k;
+
+	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+		bb_miiphy_read, bb_miiphy_write);
+
+	for (k = 0; k < 32; ++k)
+		configure_gbit_phy(k);
+
+	/* take fpga serdes blocks out of reset */
+	fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+
+	return 0;
+}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
new file mode 100644
index 0000000000..ecd6cb2396
--- /dev/null
+++ b/board/gdsys/405ep/iocon.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+#include "../common/osd.h"
+
+enum {
+	REG_VERSIONS = 0x0002,
+	REG_FPGA_VERSION = 0x0004,
+	REG_FPGA_FEATURES = 0x0006,
+};
+
+enum {
+	UNITTYPE_MAIN_SERVER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_104 = 1,
+	HWVER_110 = 2,
+};
+
+enum {
+	COMPRESSION_NONE = 0,
+	COMPRESSION_TYPE1_DELTA,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_147456 = 0,
+};
+
+enum {
+	RAM_DDR2_32 = 0,
+};
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u16 versions = fpga_get_reg(REG_VERSIONS);
+	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_compression;
+	unsigned feature_osd;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_compression = (fpga_features & 0xe000) >> 13;
+	feature_osd = fpga_features & (1<<11);
+	feature_audio = (fpga_features & 0x0600) >> 9;
+	feature_sysclock = (fpga_features & 0x0180) >> 7;
+	feature_ramconfig = (fpga_features & 0x0060) >> 5;
+	feature_carriers = (fpga_features & 0x000c) >> 2;
+	feature_video_channels = fpga_features & 0x0003;
+
+	printf("Board: ");
+
+	printf("IoCon");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	switch (unit_type) {
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel");
+		break;
+
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_104:
+		printf(" HW-Ver 1.04\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+
+	switch (feature_compression) {
+	case COMPRESSION_NONE:
+		printf(" no compression");
+		break;
+
+	case COMPRESSION_TYPE1_DELTA:
+		printf(" type1-deltacompression");
+		break;
+
+	default:
+		printf(" compression %d(not supported)", feature_compression);
+		break;
+	}
+
+	printf(", %sosd", feature_osd ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_sysclock) {
+	case SYSCLK_147456:
+		printf("clock 147.456 MHz");
+		break;
+
+	default:
+		printf("clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	switch (feature_ramconfig) {
+	case RAM_DDR2_32:
+		printf(", RAM 32 bit DDR2");
+		break;
+
+	default:
+		printf(", RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s)", feature_carriers);
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	return osd_probe();
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ */
+void fpga_gpio_set(int pin)
+{
+	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+}
+
+void fpga_gpio_clear(int pin)
+{
+	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+}
+
+int fpga_gpio_get(int pin)
+{
+	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+}