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authorMark Langsdorf <mark.langsdorf@gmail.com>2015-06-05 00:58:43 +0100
committerTom Rini <trini@konsulko.com>2015-06-12 13:02:07 -0400
commitf8973325d08c6d391ed37bb48b2cf2e1d2f8b444 (patch)
treec11a00e73a28a5b6d34e213ae3eb0b29ab6e9030 /board/highbank
parent083ffd65cb46e76a0db95403f894dbfcde2daca8 (diff)
ARM: highbank: add reset support for Calxeda Midway machine
The Calxeda Midway part has A15 cores, which do not have the Highbank A9's SCU used there for resetting the chip. Add code to distinguish between the A9 and the A15 and invoke the appropriate register writes to support the newer part. Andre: rework detection of Highbank vs. Midway Rob: fix Andre's reworked detection Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'board/highbank')
-rw-r--r--board/highbank/highbank.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index ba254b6352..e8132b842f 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -18,6 +18,7 @@
#define HB_SREG_A9_PWR_REQ 0xfff3cf00
#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
+#define HB_SREG_A15_PWR_CTRL 0xfff3c200
#define HB_PWR_SUSPEND 0
#define HB_PWR_SOFT_RESET 1
@@ -116,10 +117,22 @@ int ft_board_setup(void *fdt, bd_t *bd)
}
#endif
+static int is_highbank(void)
+{
+ uint32_t midr;
+
+ asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
+
+ return (midr & 0xfff0) == 0xc090;
+}
+
void reset_cpu(ulong addr)
{
writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
- writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+ if (is_highbank())
+ writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+ else
+ writel(0x1, HB_SREG_A15_PWR_CTRL);
wfi();
}