ARM: am335x: Add phyCORE AM335x R2 support

Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
phyBOARD-Wega AM335x.

CPU  : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-WEGA
DRAM:  256 MiB
NAND:  256 MiB
MMC:   OMAP SD/MMC: 0
eth0: ethernet@4a100000

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART
 - USB (host)

Device trees were taken from Linux mainline:
commit 37624b58542f ("Linux 5.1-rc7")

Signed-off-by: Niel Fourie <lusus@denx.de>
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Marek Vasut <marex@denx.de>

6 files changed, 434 insertions, 0 deletions

diff --git a/board/phytec/phycore_am335x_r2/Kconfig b/board/phytec/phycore_am335x_r2/Kconfig
new file mode 100644
index 0000000000..77055e043c
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PHYCORE_AM335X_R2
+
+config SYS_BOARD
+	default "phycore_am335x_r2"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "phycore_am335x_r2"
+
+endif
diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS
new file mode 100644
index 0000000000..e56f30fdc0
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/MAINTAINERS
@@ -0,0 +1,7 @@
+phyCORE AM335x R2 WEGA BOARD
+M:	Niel Fourie <lusus@denx.de>
+M:	Parthiban Nallathambi <pn@denx.de>
+S:	Maintained
+F:	board/phytec/phycore_am335x_r2
+F:	include/configs/phycore_am335x_r2.h
+F:	configs/phycore-am335x-r2-wega_defconfig
diff --git a/board/phytec/phycore_am335x_r2/Makefile b/board/phytec/phycore_am335x_r2/Makefile
new file mode 100644
index 0000000000..ff6f8b4221
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c
new file mode 100644
index 0000000000..02d6c27cec
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/board.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <power/tps65910.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <fdt_support.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ		400 /* DDR_DPLL_MULT value */
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+		DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= 0x18B,
+	.cm1ioctl		= 0x18B,
+	.cm2ioctl		= 0x18B,
+	.dt0ioctl		= 0x18B,
+	.dt1ioctl		= 0x18B,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = 0x80,
+	.cmd0iclkout = 0x0,
+
+	.cmd1csratio = 0x80,
+	.cmd1iclkout = 0x0,
+
+	.cmd2csratio = 0x80,
+	.cmd2iclkout = 0x0,
+};
+
+enum {
+	PHYCORE_R2_MT41K128M16JT_256MB,
+	PHYCORE_R2_MT41K256M16TW107IT_512MB,
+	PHYCORE_R2_MT41K512M16HA125IT_1024MB,
+};
+
+struct am335x_sdram_timings {
+	struct emif_regs ddr3_emif_reg_data;
+	struct ddr_data ddr3_data;
+};
+
+static struct am335x_sdram_timings physom_timings[] = {
+	[PHYCORE_R2_MT41K128M16JT_256MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C052B2,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x26437FDA,
+			.sdram_tim3 = 0x501F83FF,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x36,
+			.datawdsratio0 = 0x38,
+			.datafwsratio0 = 0x99,
+			.datawrsratio0 = 0x73,
+		},
+	},
+	[PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C05332,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x266B7FDA,
+			.sdram_tim3 = 0x501F867F,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x37,
+			.datawdsratio0 = 0x38,
+			.datafwsratio0 = 0x92,
+			.datawrsratio0 = 0x72,
+		},
+	},
+	[PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C053B2,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x268F7FDA,
+			.sdram_tim3 = 0x501F88BF,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x38,
+			.datawdsratio0 = 0x4d,
+			.datafwsratio0 = 0x9d,
+			.datawrsratio0 = 0x82,
+		},
+	},
+};
+
+void sdram_init(void)
+{
+	/* Configure memory to maximum supported size for detection */
+	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+
+	config_ddr(DDR_CLK_MHZ, &ioregs,
+		   &physom_timings[ram_type_index].ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
+		   0);
+
+	/* Detect memory physically present */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_MAX_RAM_BANK_SIZE);
+
+	/* Reconfigure memory for actual detected size */
+	switch (gd->ram_size) {
+	case SZ_1G:
+		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+		break;
+	case SZ_512M:
+		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
+		break;
+	case SZ_256M:
+	default:
+		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
+		break;
+	}
+	config_ddr(DDR_CLK_MHZ, &ioregs,
+		   &physom_timings[ram_type_index].ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
+		   0);
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int ind = get_sys_clk_index();
+	int freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		return &dpll_mpu_opp[ind][5];
+	case MPUPLL_M_800:
+		return &dpll_mpu_opp[ind][4];
+	case MPUPLL_M_720:
+		return &dpll_mpu_opp[ind][3];
+	case MPUPLL_M_600:
+		return &dpll_mpu_opp[ind][2];
+	case MPUPLL_M_500:
+		return &dpll_mpu_opp100;
+	case MPUPLL_M_300:
+		return &dpll_mpu_opp[ind][0];
+	}
+
+	return &dpll_mpu_opp[ind][0];
+}
+
+static void scale_vcores_generic(int freq)
+{
+	int sil_rev, mpu_vdd;
+
+	/*
+	 * We use a TPS65910 PMIC. For all  MPU frequencies we support we use a
+	 * CORE voltage of 1.10V. For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+	if (power_tps65910_init(0))
+		return;
+
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
+
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
+
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
+
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
+		return;
+}
+
+void scale_vcores(void)
+{
+	int freq;
+
+	freq = am335x_get_efuse_mpu_max_freq(cdev);
+	scale_vcores_generic(freq);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_i2c0_pin_mux();
+	enable_board_pin_mux();
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static const struct node_info nodes[] = {
+		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+	};
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+	return 0;
+}
+#endif
diff --git a/board/phytec/phycore_am335x_r2/board.h b/board/phytec/phycore_am335x_r2/board.h
new file mode 100644
index 0000000000..1b90861dd3
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/board.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (PCL060 / PCM060) boards information header
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to access the PMIC. We then have a main
+ * pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif
diff --git a/board/phytec/phycore_am335x_r2/mux.c b/board/phytec/phycore_am335x_r2/mux.c
new file mode 100644
index 0000000000..5fd452e66d
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/mux.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},     /* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},   /* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},               /* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},               /* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},               /* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN},	/* JP4 */
+	{-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+	configure_module_pin_mux(spi0_pin_mux);
+#endif
+}