diff options
| author | Stefan Mavrodiev <stefan@olimex.com> | 2019-01-08 12:04:30 +0200 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-18 22:19:08 +0530 |
| commit | da1ae5905ee84032bea187e4845a2f6743cf8ac4 (patch) | |
| tree | 5b90f14e814a4e7cd57a27ed5db392658985d069 /board/sunxi | |
| parent | f83ef0dac83110d20389eb71f09285f009f3d198 (diff) | |
sunxi: board: Add i2c initialization for sun50i
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE.
However even the controller is enabled, the mux for the pins
are not set.
This patch follows the existing mux method. Since the pads are
different, separate check is added for each i2c.
Tested with A64-SOM204 board.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'board/sunxi')
| -rw-r--r-- | board/sunxi/board.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index f022f365e9..ad14837291 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -98,6 +98,10 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); + clock_twi_onoff(0, 1); #endif #endif @@ -120,6 +124,10 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); + clock_twi_onoff(1, 1); #endif #endif @@ -142,6 +150,10 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2); + clock_twi_onoff(2, 1); #endif #endif |