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authorMax Krummenacher <max.krummenacher@toradex.com>2019-02-08 18:42:17 +0100
committerStefano Babic <sbabic@denx.de>2019-04-13 20:30:09 +0200
commit2910c0a135ecc0dcaae02503cda949376e767f8e (patch)
treebc96d848394cc9e1b5517106710d61056bb55cb2 /board/toradex/colibri_imx6/colibri_imx6.c
parent1ebb754b20402bef2b234e2fd45dd439974ad440 (diff)
colibri_imx6: print also 64-bit IT
Print also for Colibri iMX6 512MB IT with 64-bit RAM bus. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'board/toradex/colibri_imx6/colibri_imx6.c')
-rw-r--r--board/toradex/colibri_imx6/colibri_imx6.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 0802b0fade..f775e788b0 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -1028,6 +1028,7 @@ static void spl_dram_init(void)
case TEMP_AUTOMOTIVE:
default:
if (is_cpu_type(MXC_CPU_MX6DL)) {
+ puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");